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[PATCH 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
From: |
Peter Maydell |
Subject: |
[PATCH 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled |
Date: |
Fri, 27 Jan 2023 17:54:51 +0000 |
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state. We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.
Add the missing checks. (Other places where we look at HSTR_EL2
for the not-in-v8A bits TTEE and TJDBX are already checking that
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 2 +-
target/arm/op_helper.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6f6772d8e04..66966869218 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11716,7 +11716,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState
*env, int fp_el,
DP_TBFLAG_A32(flags, VFPEN, 1);
}
- if (el < 2 && env->cp15.hstr_el2 &&
+ if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
}
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 8ac176e0742..5c17a5bd176 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -670,6 +670,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env,
uint32_t key,
* we only need to check here for traps from EL0.
*/
if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
+ arm_is_el2_enabled(env) &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
uint32_t mask = 1 << ri->crn;
--
2.34.1
- [PATCH 04/23] target/arm: Move do_coproc_insn() syndrome calculation earlier, (continued)
- [PATCH 04/23] target/arm: Move do_coproc_insn() syndrome calculation earlier, Peter Maydell, 2023/01/27
- [PATCH 18/23] target/arm: Mark up sysregs for HFGITR bits 18..47, Peter Maydell, 2023/01/27
- [PATCH 12/23] target/arm: Mark up sysregs for HFGRTR bits 24..35, Peter Maydell, 2023/01/27
- [PATCH 09/23] target/arm: Implement FGT trapping infrastructure, Peter Maydell, 2023/01/27
- [PATCH 11/23] target/arm: Mark up sysregs for HFGRTR bits 12..23, Peter Maydell, 2023/01/27
- [PATCH 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled,
Peter Maydell <=
- [PATCH 21/23] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps, Peter Maydell, 2023/01/27
- [PATCH 10/23] target/arm: Mark up sysregs for HFGRTR bits 0..11, Peter Maydell, 2023/01/27
- [PATCH 16/23] target/arm: Mark up sysregs for HFGITR bits 0..11, Peter Maydell, 2023/01/27
- [PATCH 08/23] target/arm: Define the FEAT_FGT registers, Peter Maydell, 2023/01/27
- [PATCH 15/23] target/arm: Mark up sysregs for HDFGRTR bits 12..63, Peter Maydell, 2023/01/27