Re: [PATCH 2/9] igb: handle PF/VF reset properly

[Akihiko Odaki]

On 2023/01/29 14:58, Akihiko Odaki wrote:
> On 2023/01/28 22:46, Sriram Yagnaraman wrote:
> > Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF
> > is reset.
> >
> > Signed-off-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
> > ---
> >   hw/net/e1000x_regs.h |  1 +
> >   hw/net/igb_core.c    | 33 +++++++++++++++++++++------------
> >   hw/net/trace-events  |  2 ++
> >   3 files changed, 24 insertions(+), 12 deletions(-)
> >
> > diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h
> > index fb5b861135..bb3fb36b8d 100644
> > --- a/hw/net/e1000x_regs.h
> > +++ b/hw/net/e1000x_regs.h
> > @@ -548,6 +548,7 @@
> >   #define E1000_CTRL_EXT_ASDCHK  0x00001000 /* auto speed detection 
> > check */
> >   #define E1000_CTRL_EXT_EE_RST  0x00002000 /* EEPROM reset */
> > +#define E1000_CTRL_EXT_PFRSTD  0x00004000 /* PF reset done indication */
> >   #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from 
> > external LINK_0 and LINK_1 pins */
> >   #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for 
> > FW */
> >   #define E1000_CTRL_EXT_EIAME   0x01000000
> > diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
> > index abeb9c7889..9bd53cc25f 100644
> > --- a/hw/net/igb_core.c
> > +++ b/hw/net/igb_core.c
> > @@ -1902,14 +1902,6 @@ static void igb_set_eims(IGBCore *core, int 
> > index, uint32_t val)
> >       igb_update_interrupt_state(core);
> >   }
> > -static void igb_vf_reset(IGBCore *core, uint16_t vfn)
> > -{
> > -    /* TODO: Reset of the queue enable and the interrupt registers of 
> > the VF. */
> > -
> > -    core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
> > -    core->mac[V2PMAILBOX0 + vfn] = E1000_V2PMAILBOX_RSTD;
> > -}
> > -
> >   static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn)
> >   {
> >       uint32_t ent = core->mac[VTIVAR_MISC + vfn];
> > @@ -1987,6 +1979,17 @@ static void igb_set_vfmailbox(IGBCore *core, 
> > int index, uint32_t val)
> >       }
> >   }
> > +static void igb_vf_reset(IGBCore *core, uint16_t vfn)
> > +{
> > +    /* disable Rx and Tx for the VF*/
> > +    core->mac[VFTE] &= ~BIT(vfn);
> > +    core->mac[VFRE] &= ~BIT(vfn);
> > +    /* indicate VF reset to PF */
> > +    core->mac[VFLRE] |= BIT(vfn);
> > +    /* VFLRE and mailbox use the same interrupt cause */
> > +    mailbox_interrupt_to_pf(core);
> > +}
> > +
>
> Please do not move the function unless you have a legitimate reason for 
> that.

I got it. It is necessary to refer mailbox_interrupt_to_pf().

Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>

> >   static void igb_w1c(IGBCore *core, int index, uint32_t val)
> >   {
> >       core->mac[index] &= ~val;
> > @@ -2241,14 +2244,20 @@ igb_set_status(IGBCore *core, int index, 
> > uint32_t val)
> >   static void
> >   igb_set_ctrlext(IGBCore *core, int index, uint32_t val)
> >   {
> > -    trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
> > -                                     !!(val & E1000_CTRL_EXT_SPD_BYPS));
> > -
> > -    /* TODO: PFRSTD */
> > +    trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
> > +                                  !!(val & E1000_CTRL_EXT_SPD_BYPS),
> > +                                  !!(val & E1000_CTRL_EXT_PFRSTD));
> >       /* Zero self-clearing bits */
> >       val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
> >       core->mac[CTRL_EXT] = val;
> > +
> > +    if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) {
> > +        for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
> > +            core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
> > +            core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD;
> > +        }
> > +    }
> >   }
> >   static void
> > diff --git a/hw/net/trace-events b/hw/net/trace-events
> > index 2f791b9b57..e94172e748 100644
> > --- a/hw/net/trace-events
> > +++ b/hw/net/trace-events
> > @@ -281,6 +281,8 @@ igb_core_mdic_read_unhandled(uint32_t addr) "MDIC 
> > READ: PHY[%u] UNHANDLED"
> >   igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: 
> > PHY[%u] = 0x%x"
> >   igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] 
> > UNHANDLED"
> > +igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, 
> > bool pfrstd) "Set extended link params: ASD check: %d, Speed select 
> > bypass: %d, PF reset done: %d"
> > +
> >   igb_rx_desc_buff_size(uint32_t b) "buffer size: %u"
> >   igb_rx_desc_buff_write(uint64_t addr, uint16_t offset, const void* 
> > source, uint32_t len) "addr: 0x%"PRIx64", offset: %u, from: %p, 
> > length: %u"