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[PULL 03/12] qemu/bitops.h: Limit rotate amounts
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From: |
Richard Henderson |
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Subject: |
[PULL 03/12] qemu/bitops.h: Limit rotate amounts |
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Date: |
Tue, 2 May 2023 12:20:14 +0100 |
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/bitops.h | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..c443995b3b 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,8 @@ static inline unsigned long find_first_zero_bit(const
unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ shift &= 7;
+ return (word << shift) | (word >> (8 - shift));
}
/**
@@ -228,7 +229,8 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ shift &= 7;
+ return (word >> shift) | (word << (8 - shift));
}
/**
@@ -238,7 +240,8 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ shift &= 15;
+ return (word << shift) | (word >> (16 - shift));
}
/**
@@ -248,7 +251,8 @@ static inline uint16_t rol16(uint16_t word, unsigned int
shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ shift &= 15;
+ return (word >> shift) | (word << (16 - shift));
}
/**
@@ -258,7 +262,8 @@ static inline uint16_t ror16(uint16_t word, unsigned int
shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ shift &= 31;
+ return (word << shift) | (word >> (32 - shift));
}
/**
@@ -268,7 +273,8 @@ static inline uint32_t rol32(uint32_t word, unsigned int
shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ shift &= 31;
+ return (word >> shift) | (word << (32 - shift));
}
/**
@@ -278,7 +284,8 @@ static inline uint32_t ror32(uint32_t word, unsigned int
shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ shift &= 63;
+ return (word << shift) | (word >> (64 - shift));
}
/**
@@ -288,7 +295,8 @@ static inline uint64_t rol64(uint64_t word, unsigned int
shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ shift &= 63;
+ return (word >> shift) | (word << (64 - shift));
}
/**
--
2.34.1
- [PULL 00/12] tcg patch queue, Richard Henderson, 2023/05/02
- [PULL 01/12] softmmu: Tidy dirtylimit_dirty_ring_full_time, Richard Henderson, 2023/05/02
- [PULL 03/12] qemu/bitops.h: Limit rotate amounts,
Richard Henderson <=
- [PULL 02/12] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Richard Henderson, 2023/05/02
- [PULL 04/12] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers, Richard Henderson, 2023/05/02
- [PULL 05/12] tcg: Add tcg_gen_gvec_andcs, Richard Henderson, 2023/05/02
- [PULL 07/12] qemu/int128: Re-shuffle Int128Alias members, Richard Henderson, 2023/05/02
- [PULL 06/12] tcg: Add tcg_gen_gvec_rotrs, Richard Henderson, 2023/05/02
- [PULL 09/12] accel/tcg: Add cpu_ld*_code_mmu, Richard Henderson, 2023/05/02
- [PULL 08/12] migration/xbzrle: Use __attribute__((target)) for avx512, Richard Henderson, 2023/05/02
- [PULL 11/12] tcg/mips: Conditionalize tcg_out_exts_i32_i64, Richard Henderson, 2023/05/02
- [PULL 10/12] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64, Richard Henderson, 2023/05/02
- [PULL 12/12] tcg: Introduce tcg_out_movext2, Richard Henderson, 2023/05/02