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[PULL 14/35] hw/net: npcm7xx_emc: set MAC in register space
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From: |
Peter Maydell |
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Subject: |
[PULL 14/35] hw/net: npcm7xx_emc: set MAC in register space |
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Date: |
Tue, 2 May 2023 13:14:38 +0100 |
From: Patrick Venture <venture@google.com>
The MAC address set from Qemu wasn't being saved into the register space.
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: moved variable declaration to top of function]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/npcm7xx_emc.c | 32 +++++++++++++++++++++++++-------
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
index 7c86bb52e57..8156f701b07 100644
--- a/hw/net/npcm7xx_emc.c
+++ b/hw/net/npcm7xx_emc.c
@@ -98,6 +98,8 @@ static const char *emc_reg_name(int regno)
static void emc_reset(NPCM7xxEMCState *emc)
{
+ uint32_t value;
+
trace_npcm7xx_emc_reset(emc->emc_num);
memset(&emc->regs[0], 0, sizeof(emc->regs));
@@ -112,6 +114,16 @@ static void emc_reset(NPCM7xxEMCState *emc)
emc->tx_active = false;
emc->rx_active = false;
+
+ /* Set the MAC address in the register space. */
+ value = (emc->conf.macaddr.a[0] << 24) |
+ (emc->conf.macaddr.a[1] << 16) |
+ (emc->conf.macaddr.a[2] << 8) |
+ emc->conf.macaddr.a[3];
+ emc->regs[REG_CAMM_BASE] = value;
+
+ value = (emc->conf.macaddr.a[4] << 24) | (emc->conf.macaddr.a[5] << 16);
+ emc->regs[REG_CAML_BASE] = value;
}
static void npcm7xx_emc_reset(DeviceState *dev)
@@ -432,13 +444,25 @@ static bool emc_receive_filter1(NPCM7xxEMCState *emc,
const uint8_t *buf,
}
case ETH_PKT_UCAST: {
bool matches;
+ uint32_t value;
+ struct MACAddr mac;
if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) {
return true;
}
+
+ value = emc->regs[REG_CAMM_BASE];
+ mac.a[0] = value >> 24;
+ mac.a[1] = value >> 16;
+ mac.a[2] = value >> 8;
+ mac.a[3] = value >> 0;
+ value = emc->regs[REG_CAML_BASE];
+ mac.a[4] = value >> 24;
+ mac.a[5] = value >> 16;
+
matches = ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) &&
/* We only support one CAM register, CAM0. */
(emc->regs[REG_CAMEN] & (1 << 0)) &&
- memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) == 0);
+ memcmp(buf, mac.a, ETH_ALEN) == 0);
if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) {
*fail_reason = "MACADDR matched, comparison complemented";
return !matches;
@@ -661,15 +685,9 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
break;
case REG_CAMM_BASE + 0:
emc->regs[reg] = value;
- emc->conf.macaddr.a[0] = value >> 24;
- emc->conf.macaddr.a[1] = value >> 16;
- emc->conf.macaddr.a[2] = value >> 8;
- emc->conf.macaddr.a[3] = value >> 0;
break;
case REG_CAML_BASE + 0:
emc->regs[reg] = value;
- emc->conf.macaddr.a[4] = value >> 24;
- emc->conf.macaddr.a[5] = value >> 16;
break;
case REG_MCMDR: {
uint32_t prev;
--
2.34.1
- [PULL 00/35] target-arm queue, Peter Maydell, 2023/05/02
- [PULL 01/35] target/arm: Move cortex sysregs into a separate file, Peter Maydell, 2023/05/02
- [PULL 02/35] target/arm: Remove dead code from cpu_max_set_sve_max_vq, Peter Maydell, 2023/05/02
- [PULL 09/35] tests/avocado: Pass parameters to migration test, Peter Maydell, 2023/05/02
- [PULL 03/35] target/arm: Extract TCG -cpu max code into a function, Peter Maydell, 2023/05/02
- [PULL 04/35] target/arm: Do not expose all -cpu max features to qtests, Peter Maydell, 2023/05/02
- [PULL 15/35] hw/arm/bcm2835_property: Implement "get command line" message, Peter Maydell, 2023/05/02
- [PULL 28/35] hw/arm/boot: Make write_bootloader() public as arm_write_bootloader(), Peter Maydell, 2023/05/02
- [PULL 26/35] docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation, Peter Maydell, 2023/05/02
- [PULL 25/35] qmp: Deprecate 'singlestep' member of StatusInfo, Peter Maydell, 2023/05/02
- [PULL 14/35] hw/net: npcm7xx_emc: set MAC in register space,
Peter Maydell <=
- [PULL 27/35] hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc(), Peter Maydell, 2023/05/02
- [PULL 23/35] hmp: Add 'one-insn-per-tb' command equivalent to 'singlestep', Peter Maydell, 2023/05/02
- [PULL 16/35] make one-insn-per-tb an accel option, Peter Maydell, 2023/05/02
- [PULL 31/35] hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit(), Peter Maydell, 2023/05/02
- [PULL 33/35] target/arm: Add compile time asserts to load/store_cpu_field macros, Peter Maydell, 2023/05/02
- [PULL 24/35] qapi/run-state.json: Fix missing newline at end of file, Peter Maydell, 2023/05/02
- [PULL 32/35] target/arm: Define and use new load_cpu_field_low32(), Peter Maydell, 2023/05/02
- [PULL 05/35] target/arm: Move 64-bit TCG CPUs into tcg/, Peter Maydell, 2023/05/02
- [PULL 22/35] accel/tcg: Report one-insn-per-tb in 'info jit', not 'info status', Peter Maydell, 2023/05/02
- [PULL 10/35] arm/Kconfig: Always select SEMIHOSTING when TCG is present, Peter Maydell, 2023/05/02