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[PULL v2 03/12] qemu/bitops.h: Limit rotate amounts
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From: |
Richard Henderson |
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Subject: |
[PULL v2 03/12] qemu/bitops.h: Limit rotate amounts |
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Date: |
Wed, 3 May 2023 08:20:51 +0100 |
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
[rth: Mask shifts in both directions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/bitops.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..cb3526d1f4 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,7 @@ static inline unsigned long find_first_zero_bit(const
unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ return (word << (shift & 7)) | (word >> (-shift & 7));
}
/**
@@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ return (word >> (shift & 7)) | (word << (-shift & 7));
}
/**
@@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ return (word << (shift & 15)) | (word >> (-shift & 15));
}
/**
@@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int
shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ return (word >> (shift & 15)) | (word << (-shift & 15));
}
/**
@@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int
shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ return (word << (shift & 31)) | (word >> (-shift & 31));
}
/**
@@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int
shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ return (word >> (shift & 31)) | (word << (-shift & 31));
}
/**
@@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int
shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ return (word << (shift & 63)) | (word >> (-shift & 63));
}
/**
@@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int
shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ return (word >> (shift & 63)) | (word << (-shift & 63));
}
/**
--
2.34.1
- [PATCH 06/84] tcg: Widen tcg_gen_code pc_start argument to uint64_t, (continued)
- [PATCH 06/84] tcg: Widen tcg_gen_code pc_start argument to uint64_t, Richard Henderson, 2023/05/03
- [PULL v2 05/12] tcg: Add tcg_gen_gvec_andcs, Richard Henderson, 2023/05/03
- [PULL v2 01/12] softmmu: Tidy dirtylimit_dirty_ring_full_time, Richard Henderson, 2023/05/03
- [PULL v2 02/12] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Richard Henderson, 2023/05/03
- [PATCH 01/84] tcg: Split out memory ops to tcg-op-ldst.c, Richard Henderson, 2023/05/03
- [PATCH 09/84] tcg: Reduce copies for plugin_gen_mem_callbacks, Richard Henderson, 2023/05/03
- [PULL v2 06/12] tcg: Add tcg_gen_gvec_rotrs, Richard Henderson, 2023/05/03
- [PULL v2 07/12] qemu/int128: Re-shuffle Int128Alias members, Richard Henderson, 2023/05/03
- [PATCH 10/84] accel/tcg: Widen plugin_gen_empty_mem_callback to i64, Richard Henderson, 2023/05/03
- [PULL v2 04/12] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers, Richard Henderson, 2023/05/03
- [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts,
Richard Henderson <=
- [PATCH 05/84] tcg: Widen helper_atomic_* addresses to uint64_t, Richard Henderson, 2023/05/03
- [PATCH 07/84] accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback, Richard Henderson, 2023/05/03
- [PULL v2 09/12] accel/tcg: Add cpu_ld*_code_mmu, Richard Henderson, 2023/05/03
- [PULL v2 08/12] migration/xbzrle: Use __attribute__((target)) for avx512, Richard Henderson, 2023/05/03
- [PULL v2 10/12] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64, Richard Henderson, 2023/05/03