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[PATCH 26/84] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL
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From: |
Richard Henderson |
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Subject: |
[PATCH 26/84] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL |
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Date: |
Wed, 3 May 2023 08:22:33 +0100 |
All uses replaced with TCGContext.addr_type.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 16e35ea6a6..fdc1faab1b 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -908,6 +908,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
TCGReg addr_reg, MemOpIdx oi,
bool is_ld)
{
+ TCGType addr_type = s->addr_type;
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
MemOp a_bits, atom_a, atom_u;
@@ -950,19 +951,19 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
addr_adj = addr_reg;
if (a_bits < s_bits) {
addr_adj = TCG_REG_TMP0;
- tcg_out_opc_imm(s, TARGET_LONG_BITS == 32 ? OPC_ADDIW : OPC_ADDI,
+ tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI,
addr_adj, addr_reg, s_mask - a_mask);
}
compare_mask = TARGET_PAGE_MASK | a_mask;
if (compare_mask == sextreg(compare_mask, 0, 12)) {
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask);
} else {
- tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
+ tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask);
tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj);
}
/* Load the tlb comparator and the addend. */
- tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
+ tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
is_ld ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
@@ -974,7 +975,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
/* TLB Hit - translate address using addend. */
addr_adj = addr_reg;
- if (TARGET_LONG_BITS == 32) {
+ if (addr_type == TCG_TYPE_I32) {
addr_adj = TCG_REG_TMP0;
tcg_out_ext32u(s, addr_adj, addr_reg);
}
@@ -996,7 +997,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
}
TCGReg base = addr_reg;
- if (TARGET_LONG_BITS == 32) {
+ if (addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_REG_TMP0, base);
base = TCG_REG_TMP0;
}
--
2.34.1
- [PATCH 36/84] tcg: Split out tcg/debug-assert.h, (continued)
- [PATCH 36/84] tcg: Split out tcg/debug-assert.h, Richard Henderson, 2023/05/03
- [PATCH 38/84] *: Add missing includes of tcg/debug-assert.h, Richard Henderson, 2023/05/03
- [PATCH 13/84] tcg: Remove TCGv from tcg_gen_atomic_*, Richard Henderson, 2023/05/03
- [PATCH 16/84] tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32, Richard Henderson, 2023/05/03
- [PATCH 03/84] accel/tcg: Widen tcg-ldst.h addresses to uint64_t, Richard Henderson, 2023/05/03
- [PATCH 23/84] tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/03
- [PATCH 26/84] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL,
Richard Henderson <=
- [PATCH 21/84] tcg/aarch64: Remove USE_GUEST_BASE, Richard Henderson, 2023/05/03
- [PATCH 29/84] tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/03
- [PATCH 32/84] tcg: Add tlb_dyn_max_bits to TCGContext, Richard Henderson, 2023/05/03
- [PATCH 35/84] tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS, Richard Henderson, 2023/05/03
- [PATCH 39/84] *: Add missing includes of tcg/tcg.h, Richard Henderson, 2023/05/03
- [PATCH 33/84] tcg: Widen CPUTLBEntry comparators to 64-bits, Richard Henderson, 2023/05/03
- [PATCH 11/84] tcg: Add addr_type to TCGContext, Richard Henderson, 2023/05/03