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[PATCH 01/11] disas/riscv: Decode czero.{eqz,nez}
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From: |
Richard Henderson |
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Subject: |
[PATCH 01/11] disas/riscv: Decode czero.{eqz,nez} |
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Date: |
Wed, 3 May 2023 09:56:47 +0100 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index d6b0fbe5e8..c0a8b1006a 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -935,6 +935,8 @@ typedef enum {
rv_op_vsetvli = 766,
rv_op_vsetivli = 767,
rv_op_vsetvl = 768,
+ rv_op_czero_eqz = 769,
+ rv_op_czero_nez = 770,
} rv_op;
/* structures */
@@ -2066,7 +2068,9 @@ const rv_opcode_data opcode_data[] = {
{ "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8,
rv_op_vsext_vf8, 0 },
{ "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli,
rv_op_vsetvli, 0 },
{ "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli,
rv_op_vsetivli, 0 },
- { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl,
rv_op_vsetvl, 0 }
+ { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl,
rv_op_vsetvl, 0 },
+ { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -2792,6 +2796,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 45: op = rv_op_minu; break;
case 46: op = rv_op_max; break;
case 47: op = rv_op_maxu; break;
+ case 075: op = rv_op_czero_eqz; break;
+ case 077: op = rv_op_czero_nez; break;
case 130: op = rv_op_sh1add; break;
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
--
2.34.1
- [PATCH 00/11] tcg/riscv: Support for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/03
- [PATCH 03/11] tcg/riscv: Support ANDN, ORN, XNOR from Zbb, Richard Henderson, 2023/05/03
- [PATCH 06/11] tcg/riscv: Support rotates from Zbb, Richard Henderson, 2023/05/03
- [PATCH 01/11] disas/riscv: Decode czero.{eqz,nez},
Richard Henderson <=
- [PATCH 02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/03
- [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Richard Henderson, 2023/05/03
- Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Daniel Henrique Barboza, 2023/05/08
- Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Alistair Francis, 2023/05/16
- [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation, Richard Henderson, 2023/05/03