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[PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba
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From: |
Richard Henderson |
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Subject: |
[PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb |
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Date: |
Wed, 3 May 2023 09:56:50 +0100 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index c5b060023f..53a7f97b29 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -593,26 +593,42 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret,
TCGReg arg)
static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
{
- tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
- tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
+ if (have_zbb) {
+ tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
+ } else {
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
+ }
}
static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
{
- tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
- tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+ if (have_zba) {
+ tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
+ } else {
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
+ tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+ }
}
static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
- tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
+ if (have_zbb) {
+ tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
+ } else {
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
+ }
}
static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
- tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
+ if (have_zbb) {
+ tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
+ } else {
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
+ }
}
static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
--
2.34.1
- Re: [PATCH 03/11] tcg/riscv: Support ANDN, ORN, XNOR from Zbb, (continued)
- [PATCH 06/11] tcg/riscv: Support rotates from Zbb, Richard Henderson, 2023/05/03
- [PATCH 01/11] disas/riscv: Decode czero.{eqz,nez}, Richard Henderson, 2023/05/03
- [PATCH 02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/03
- [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb,
Richard Henderson <=
- Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Daniel Henrique Barboza, 2023/05/08
- Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Alistair Francis, 2023/05/16
- [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation, Richard Henderson, 2023/05/03
- [PATCH 07/11] tcg/riscv: Support REV8 from Zbb, Richard Henderson, 2023/05/03
- [PATCH 09/11] tcg/riscv: Improve setcond expansion, Richard Henderson, 2023/05/03