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[PULL 02/89] target/riscv: Fix priv version dependency for vector and zf
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From: |
Alistair Francis |
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Subject: |
[PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh |
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Date: |
Fri, 5 May 2023 11:01:14 +1000 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..eaf75a00a6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -84,7 +84,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0,
ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
- ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
+ ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
@@ -104,9 +104,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
- ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
- ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
- ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
+ ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f),
+ ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f),
+ ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d),
ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
--
2.40.0
- [PULL 00/89] riscv-to-apply queue, Alistair Francis, 2023/05/04
- [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig, Alistair Francis, 2023/05/04
- [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh,
Alistair Francis <=
- [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env, Alistair Francis, 2023/05/04
- [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState, Alistair Francis, 2023/05/04
- [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check, Alistair Francis, 2023/05/04
- [PULL 06/89] target/riscv: refactor Zicond support, Alistair Francis, 2023/05/04
- [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions, Alistair Francis, 2023/05/04
- [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry, Alistair Francis, 2023/05/04
- [PULL 09/89] target/riscv: add cfg properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 10/89] target/riscv: add support for Zca extension, Alistair Francis, 2023/05/04
- [PULL 11/89] target/riscv: add support for Zcf extension, Alistair Francis, 2023/05/04
- [PULL 12/89] target/riscv: add support for Zcd extension, Alistair Francis, 2023/05/04