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[PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env
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From: |
Alistair Francis |
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Subject: |
[PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env |
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Date: |
Fri, 5 May 2023 11:01:15 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index b8e56d2b7b..a200741083 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
return true;
}
- cpu = RISCV_CPU(env_cpu(env));
+ cpu = env_archcpu(env);
if (!cpu->pmu_event_ctr_map) {
return false;
}
@@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
uint32_t target_ctr)
return true;
}
- cpu = RISCV_CPU(env_cpu(env));
+ cpu = env_archcpu(env);
if (!cpu->pmu_event_ctr_map) {
return false;
}
@@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t
value,
uint32_t ctr_idx)
{
uint32_t event_idx;
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ RISCVCPU *cpu = env_archcpu(env);
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
return -1;
@@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t
value, uint32_t ctr_idx)
{
uint64_t overflow_delta, overflow_at;
int64_t overflow_ns, overflow_left = 0;
- RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ RISCVCPU *cpu = env_archcpu(env);
PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
--
2.40.0
- [PULL 00/89] riscv-to-apply queue, Alistair Francis, 2023/05/04
- [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig, Alistair Francis, 2023/05/04
- [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh, Alistair Francis, 2023/05/04
- [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env,
Alistair Francis <=
- [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState, Alistair Francis, 2023/05/04
- [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check, Alistair Francis, 2023/05/04
- [PULL 06/89] target/riscv: refactor Zicond support, Alistair Francis, 2023/05/04
- [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions, Alistair Francis, 2023/05/04
- [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry, Alistair Francis, 2023/05/04
- [PULL 09/89] target/riscv: add cfg properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 10/89] target/riscv: add support for Zca extension, Alistair Francis, 2023/05/04
- [PULL 11/89] target/riscv: add support for Zcf extension, Alistair Francis, 2023/05/04
- [PULL 12/89] target/riscv: add support for Zcd extension, Alistair Francis, 2023/05/04
- [PULL 13/89] target/riscv: add support for Zcb extension, Alistair Francis, 2023/05/04