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[PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entr
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From: |
Alistair Francis |
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Subject: |
[PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry |
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Date: |
Fri, 5 May 2023 11:01:20 +1000 |
From: Conor Dooley <conor.dooley@microchip.com>
dt-validate complains:
> soc: pmu: {'riscv,event-to-mhpmcounters':
> [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280],
> [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]],
> pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short
There are bogus 0 entries added at the end, of which one is of
insufficient length. This happens because only 15 of
fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is
called using the size of the array.
Reduce the array to 15 elements to make the error go away.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230404173333.35179-1-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 22e2283c76..96ce2dbe49 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -35,7 +35,7 @@
*/
void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
{
- uint32_t fdt_event_ctr_map[20] = {};
+ uint32_t fdt_event_ctr_map[15] = {};
uint32_t cmask;
/* All the programmable counters can map to any event */
--
2.40.0
- [PULL 00/89] riscv-to-apply queue, Alistair Francis, 2023/05/04
- [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig, Alistair Francis, 2023/05/04
- [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh, Alistair Francis, 2023/05/04
- [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env, Alistair Francis, 2023/05/04
- [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState, Alistair Francis, 2023/05/04
- [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check, Alistair Francis, 2023/05/04
- [PULL 06/89] target/riscv: refactor Zicond support, Alistair Francis, 2023/05/04
- [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions, Alistair Francis, 2023/05/04
- [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry,
Alistair Francis <=
- [PULL 09/89] target/riscv: add cfg properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 10/89] target/riscv: add support for Zca extension, Alistair Francis, 2023/05/04
- [PULL 11/89] target/riscv: add support for Zcf extension, Alistair Francis, 2023/05/04
- [PULL 12/89] target/riscv: add support for Zcd extension, Alistair Francis, 2023/05/04
- [PULL 13/89] target/riscv: add support for Zcb extension, Alistair Francis, 2023/05/04
- [PULL 14/89] target/riscv: add support for Zcmp extension, Alistair Francis, 2023/05/04
- [PULL 15/89] target/riscv: add support for Zcmt extension, Alistair Francis, 2023/05/04
- [PULL 16/89] target/riscv: expose properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 17/89] disas/riscv.c: add disasm support for Zc*, Alistair Francis, 2023/05/04
- [PULL 18/89] target/riscv: Add support for Zce, Alistair Francis, 2023/05/04