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[PULL 12/89] target/riscv: add support for Zcd extension
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From: |
Alistair Francis |
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Subject: |
[PULL 12/89] target/riscv: add support for Zcd extension |
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Date: |
Fri, 5 May 2023 11:01:24 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16.decode | 8 ++++----
target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++++++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index f3ea650325..b62664b6af 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -97,12 +97,12 @@
}
{
lq 001 ... ... .. ... 00 @cl_q
- fld 001 ... ... .. ... 00 @cl_d
+ c_fld 001 ... ... .. ... 00 @cl_d
}
lw 010 ... ... .. ... 00 @cl_w
{
sq 101 ... ... .. ... 00 @cs_q
- fsd 101 ... ... .. ... 00 @cs_d
+ c_fsd 101 ... ... .. ... 00 @cs_d
}
sw 110 ... ... .. ... 00 @cs_w
@@ -148,7 +148,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2
slli 000 . ..... ..... 10 @c_shift2
{
lq 001 ... ... .. ... 10 @c_lqsp
- fld 001 . ..... ..... 10 @c_ldsp
+ c_fld 001 . ..... ..... 10 @c_ldsp
}
{
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
@@ -166,7 +166,7 @@ slli 000 . ..... ..... 10 @c_shift2
}
{
sq 101 ... ... .. ... 10 @c_sqsp
- fsd 101 ...... ..... 10 @c_sdsp
+ c_fsd 101 ...... ..... 10 @c_sdsp
}
sw 110 . ..... ..... 10 @c_swsp
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index 1597bf31d8..2c51e01c40 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -31,6 +31,12 @@
} \
} while (0)
+#define REQUIRE_ZCD(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcd) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
TCGv addr;
@@ -59,6 +65,18 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
return true;
}
+static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
+{
+ REQUIRE_ZCD(ctx);
+ return trans_fld(ctx, a);
+}
+
+static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
+{
+ REQUIRE_ZCD(ctx);
+ return trans_fsd(ctx, a);
+}
+
static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
{
REQUIRE_FPU;
--
2.40.0
- [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh, (continued)
- [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh, Alistair Francis, 2023/05/04
- [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env, Alistair Francis, 2023/05/04
- [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState, Alistair Francis, 2023/05/04
- [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check, Alistair Francis, 2023/05/04
- [PULL 06/89] target/riscv: refactor Zicond support, Alistair Francis, 2023/05/04
- [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions, Alistair Francis, 2023/05/04
- [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry, Alistair Francis, 2023/05/04
- [PULL 09/89] target/riscv: add cfg properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 10/89] target/riscv: add support for Zca extension, Alistair Francis, 2023/05/04
- [PULL 11/89] target/riscv: add support for Zcf extension, Alistair Francis, 2023/05/04
- [PULL 12/89] target/riscv: add support for Zcd extension,
Alistair Francis <=
- [PULL 13/89] target/riscv: add support for Zcb extension, Alistair Francis, 2023/05/04
- [PULL 14/89] target/riscv: add support for Zcmp extension, Alistair Francis, 2023/05/04
- [PULL 15/89] target/riscv: add support for Zcmt extension, Alistair Francis, 2023/05/04
- [PULL 16/89] target/riscv: expose properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 17/89] disas/riscv.c: add disasm support for Zc*, Alistair Francis, 2023/05/04
- [PULL 18/89] target/riscv: Add support for Zce, Alistair Francis, 2023/05/04
- [PULL 19/89] target/riscv: Fix itrigger when icount is used, Alistair Francis, 2023/05/04
- [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04