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[PULL 16/89] target/riscv: expose properties for Zc* extension
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From: |
Alistair Francis |
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Subject: |
[PULL 16/89] target/riscv: expose properties for Zc* extension |
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Date: |
Fri, 5 May 2023 11:01:28 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 97b0a77d8e..ed8dc61d10 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -87,6 +87,12 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
+ ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
+ ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
+ ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
+ ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
+ ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
+ ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
@@ -1491,6 +1497,14 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+
+ DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
+ DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
+ DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
+ DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
+ DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
+ DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
+
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
--
2.40.0
- [PULL 06/89] target/riscv: refactor Zicond support, (continued)
- [PULL 06/89] target/riscv: refactor Zicond support, Alistair Francis, 2023/05/04
- [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions, Alistair Francis, 2023/05/04
- [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry, Alistair Francis, 2023/05/04
- [PULL 09/89] target/riscv: add cfg properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 10/89] target/riscv: add support for Zca extension, Alistair Francis, 2023/05/04
- [PULL 11/89] target/riscv: add support for Zcf extension, Alistair Francis, 2023/05/04
- [PULL 12/89] target/riscv: add support for Zcd extension, Alistair Francis, 2023/05/04
- [PULL 13/89] target/riscv: add support for Zcb extension, Alistair Francis, 2023/05/04
- [PULL 14/89] target/riscv: add support for Zcmp extension, Alistair Francis, 2023/05/04
- [PULL 15/89] target/riscv: add support for Zcmt extension, Alistair Francis, 2023/05/04
- [PULL 16/89] target/riscv: expose properties for Zc* extension,
Alistair Francis <=
- [PULL 17/89] disas/riscv.c: add disasm support for Zc*, Alistair Francis, 2023/05/04
- [PULL 18/89] target/riscv: Add support for Zce, Alistair Francis, 2023/05/04
- [PULL 19/89] target/riscv: Fix itrigger when icount is used, Alistair Francis, 2023/05/04
- [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 21/89] target/riscv: Remove redundant check on RVH, Alistair Francis, 2023/05/04
- [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled, Alistair Francis, 2023/05/04