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[PULL 26/89] target/riscv: Fix addr type for get_physical_address
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From: |
Alistair Francis |
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Subject: |
[PULL 26/89] target/riscv: Fix addr type for get_physical_address |
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Date: |
Fri, 5 May 2023 11:01:38 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Function get_physical_address() translates both virtual address and
guest physical address, and the latter is 34-bits for Sv32x4. So we
should use vaddr type for 'addr' parameter.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9e2be29c45..b0e094a933 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -732,7 +732,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int
*prot,
* @env: CPURISCVState
* @physical: This will be set to the calculated physical address
* @prot: The returned protection attributes
- * @addr: The virtual address to be translated
+ * @addr: The virtual address or guest physical address to be translated
* @fault_pte_addr: If not NULL, this will be set to fault pte address
* when a error occurs on pte address translation.
* This will already be shifted to match htval.
@@ -744,7 +744,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int
*prot,
* @is_debug: Is this access from a debugger or the monitor?
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
- int *prot, target_ulong addr,
+ int *prot, vaddr addr,
target_ulong *fault_pte_addr,
int access_type, int mmu_idx,
bool first_stage, bool two_stage,
--
2.40.0
- [PULL 18/89] target/riscv: Add support for Zce, (continued)
- [PULL 18/89] target/riscv: Add support for Zce, Alistair Francis, 2023/05/04
- [PULL 19/89] target/riscv: Fix itrigger when icount is used, Alistair Francis, 2023/05/04
- [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 21/89] target/riscv: Remove redundant check on RVH, Alistair Francis, 2023/05/04
- [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled, Alistair Francis, 2023/05/04
- [PULL 25/89] target/riscv: Remove redundant parentheses, Alistair Francis, 2023/05/04
- [PULL 26/89] target/riscv: Fix addr type for get_physical_address,
Alistair Francis <=
- [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault, Alistair Francis, 2023/05/04
- [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled(), Alistair Francis, 2023/05/04
- [PULL 29/89] target/riscv: Fix format for indentation, Alistair Francis, 2023/05/04
- [PULL 31/89] target/riscv: Fix lines with over 80 characters, Alistair Francis, 2023/05/04
- [PULL 30/89] target/riscv: Fix format for comments, Alistair Francis, 2023/05/04
- [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests, Alistair Francis, 2023/05/04
- [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize(), Alistair Francis, 2023/05/04
- [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[], Alistair Francis, 2023/05/04
- [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data, Alistair Francis, 2023/05/04
- [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties(), Alistair Francis, 2023/05/04