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[PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual i
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From: |
Alistair Francis |
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Subject: |
[PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault |
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Date: |
Fri, 5 May 2023 11:01:39 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc
b/target/riscv/insn_trans/trans_rvh.c.inc
index 9248b48c36..4b730cd492 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -20,6 +20,8 @@
static bool check_access(DisasContext *ctx)
{
if (!ctx->hlsx) {
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ offsetof(CPURISCVState, bins));
if (ctx->virt_enabled) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {
--
2.40.0
- [PULL 19/89] target/riscv: Fix itrigger when icount is used, (continued)
- [PULL 19/89] target/riscv: Fix itrigger when icount is used, Alistair Francis, 2023/05/04
- [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 21/89] target/riscv: Remove redundant check on RVH, Alistair Francis, 2023/05/04
- [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled, Alistair Francis, 2023/05/04
- [PULL 25/89] target/riscv: Remove redundant parentheses, Alistair Francis, 2023/05/04
- [PULL 26/89] target/riscv: Fix addr type for get_physical_address, Alistair Francis, 2023/05/04
- [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault,
Alistair Francis <=
- [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled(), Alistair Francis, 2023/05/04
- [PULL 29/89] target/riscv: Fix format for indentation, Alistair Francis, 2023/05/04
- [PULL 31/89] target/riscv: Fix lines with over 80 characters, Alistair Francis, 2023/05/04
- [PULL 30/89] target/riscv: Fix format for comments, Alistair Francis, 2023/05/04
- [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests, Alistair Francis, 2023/05/04
- [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize(), Alistair Francis, 2023/05/04
- [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[], Alistair Francis, 2023/05/04
- [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data, Alistair Francis, 2023/05/04
- [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties(), Alistair Francis, 2023/05/04
- [PULL 38/89] target/riscv: remove cpu->cfg.ext_c, Alistair Francis, 2023/05/04