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[PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[]
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From: |
Alistair Francis |
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Subject: |
[PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[] |
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Date: |
Fri, 5 May 2023 11:01:46 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related verifications in a new function, removing it from
isa_edata_arr[].
We're also erroring it out instead of disabling, making the cpu_init()
function responsible for running an adequate priv spec for the MISA
extensions it wants to use.
Note that the RVV verification is being ignored since we're always have
at least PRIV_VERSION_1_10_0.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 66de3bb33f..ed8f36c649 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -72,10 +72,11 @@ struct isa_ext_data {
* 4. Non-standard extensions (starts with 'X') must be listed after all
* standard extensions. They must be separated from other multi-letter
* extensions by an underscore.
+ *
+ * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
+ * instead.
*/
static const struct isa_ext_data isa_edata_arr[] = {
- ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
- ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
@@ -1191,6 +1192,14 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
env->misa_ext = env->misa_ext_mask = ext;
}
+static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
+{
+ if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
+ error_setg(errp, "H extension requires priv spec 1.12.0");
+ return;
+ }
+}
+
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -1234,6 +1243,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
*/
riscv_cpu_sync_misa_cfg(env);
+ riscv_cpu_validate_misa_priv(env, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
/* Force disable extensions if priv spec version does not match */
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
--
2.40.0
- [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled, (continued)
- [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled, Alistair Francis, 2023/05/04
- [PULL 25/89] target/riscv: Remove redundant parentheses, Alistair Francis, 2023/05/04
- [PULL 26/89] target/riscv: Fix addr type for get_physical_address, Alistair Francis, 2023/05/04
- [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault, Alistair Francis, 2023/05/04
- [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled(), Alistair Francis, 2023/05/04
- [PULL 29/89] target/riscv: Fix format for indentation, Alistair Francis, 2023/05/04
- [PULL 31/89] target/riscv: Fix lines with over 80 characters, Alistair Francis, 2023/05/04
- [PULL 30/89] target/riscv: Fix format for comments, Alistair Francis, 2023/05/04
- [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests, Alistair Francis, 2023/05/04
- [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize(), Alistair Francis, 2023/05/04
- [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[],
Alistair Francis <=
- [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data, Alistair Francis, 2023/05/04
- [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties(), Alistair Francis, 2023/05/04
- [PULL 38/89] target/riscv: remove cpu->cfg.ext_c, Alistair Francis, 2023/05/04
- [PULL 39/89] target/riscv: remove cpu->cfg.ext_d, Alistair Francis, 2023/05/04
- [PULL 40/89] target/riscv: remove cpu->cfg.ext_f, Alistair Francis, 2023/05/04
- [PULL 37/89] target/riscv: remove cpu->cfg.ext_a, Alistair Francis, 2023/05/04
- [PULL 42/89] target/riscv: remove cpu->cfg.ext_e, Alistair Francis, 2023/05/04
- Re: [PULL 00/89] riscv-to-apply queue, Alistair Francis, 2023/05/04
- [PULL 43/89] target/riscv: remove cpu->cfg.ext_m, Alistair Francis, 2023/05/04