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[PULL 47/89] target/riscv: remove cpu->cfg.ext_j
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From: |
Alistair Francis |
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Subject: |
[PULL 47/89] target/riscv: remove cpu->cfg.ext_j |
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Date: |
Fri, 5 May 2023 11:01:59 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 6 +++---
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 823be82239..1aff93ba91 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6291224905..3bdd6875a8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1178,7 +1178,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_v) {
ext |= RVV;
}
- if (riscv_cpu_cfg(env)->ext_j) {
+ if (riscv_has_ext(env, RVJ)) {
ext |= RVJ;
}
@@ -1511,6 +1511,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVU, .enabled = true},
{.name = "h", .description = "Hypervisor",
.misa_bit = RVH, .enabled = true},
+ {.name = "x-j", .description = "Dynamic translated languages",
+ .misa_bit = RVJ, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1607,7 +1609,6 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
- DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
@@ -1648,7 +1649,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_j = misa_ext & RVJ;
/*
* We don't want to set the default riscv_cpu_extensions
--
2.40.0
- [PULL 42/89] target/riscv: remove cpu->cfg.ext_e, (continued)
- [PULL 42/89] target/riscv: remove cpu->cfg.ext_e, Alistair Francis, 2023/05/04
- Re: [PULL 00/89] riscv-to-apply queue, Alistair Francis, 2023/05/04
- [PULL 43/89] target/riscv: remove cpu->cfg.ext_m, Alistair Francis, 2023/05/04
- [PULL 41/89] target/riscv: remove cpu->cfg.ext_i, Alistair Francis, 2023/05/04
- [PULL 45/89] target/riscv: remove cpu->cfg.ext_u, Alistair Francis, 2023/05/04
- [PULL 44/89] target/riscv: remove cpu->cfg.ext_s, Alistair Francis, 2023/05/04
- [PULL 46/89] target/riscv: remove cpu->cfg.ext_h, Alistair Francis, 2023/05/04
- [PULL 48/89] target/riscv: remove cpu->cfg.ext_v, Alistair Francis, 2023/05/04
- [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg(), Alistair Francis, 2023/05/04
- [PULL 47/89] target/riscv: remove cpu->cfg.ext_j,
Alistair Francis <=
- [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g, Alistair Francis, 2023/05/04
- [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props(), Alistair Francis, 2023/05/04
- [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Alistair Francis, 2023/05/04
- [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET, Alistair Francis, 2023/05/04
- [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H, Alistair Francis, 2023/05/04
- [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus, Alistair Francis, 2023/05/04
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx, Alistair Francis, 2023/05/04
- [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags, Alistair Francis, 2023/05/04
- [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Alistair Francis, 2023/05/04
- [PULL 58/89] target/riscv: Extract virt enabled state from tb flags, Alistair Francis, 2023/05/04