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[PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRE
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From: |
Alistair Francis |
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Subject: |
[PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET |
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Date: |
Fri, 5 May 2023 11:02:05 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230407014743.18779-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ec9a384772..b8a03afebb 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -338,7 +338,8 @@ target_ulong helper_mret(CPURISCVState *env)
mstatus = set_field(mstatus, MSTATUS_MIE,
get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
- mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
+ mstatus = set_field(mstatus, MSTATUS_MPP,
+ riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
--
2.40.0
- [PULL 41/89] target/riscv: remove cpu->cfg.ext_i, (continued)
- [PULL 41/89] target/riscv: remove cpu->cfg.ext_i, Alistair Francis, 2023/05/04
- [PULL 45/89] target/riscv: remove cpu->cfg.ext_u, Alistair Francis, 2023/05/04
- [PULL 44/89] target/riscv: remove cpu->cfg.ext_s, Alistair Francis, 2023/05/04
- [PULL 46/89] target/riscv: remove cpu->cfg.ext_h, Alistair Francis, 2023/05/04
- [PULL 48/89] target/riscv: remove cpu->cfg.ext_v, Alistair Francis, 2023/05/04
- [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg(), Alistair Francis, 2023/05/04
- [PULL 47/89] target/riscv: remove cpu->cfg.ext_j, Alistair Francis, 2023/05/04
- [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g, Alistair Francis, 2023/05/04
- [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props(), Alistair Francis, 2023/05/04
- [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Alistair Francis, 2023/05/04
- [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET,
Alistair Francis <=
- [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H, Alistair Francis, 2023/05/04
- [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus, Alistair Francis, 2023/05/04
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx, Alistair Francis, 2023/05/04
- [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags, Alistair Francis, 2023/05/04
- [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Alistair Francis, 2023/05/04
- [PULL 58/89] target/riscv: Extract virt enabled state from tb flags, Alistair Francis, 2023/05/04
- [PULL 57/89] target/riscv: fix H extension TVM trap, Alistair Francis, 2023/05/04
- [PULL 59/89] target/riscv: Add a general status enum for extensions, Alistair Francis, 2023/05/04
- [PULL 62/89] target/riscv: Add a tb flags field for vstart, Alistair Francis, 2023/05/04
- [PULL 63/89] target/riscv: Separate priv from mmu_idx, Alistair Francis, 2023/05/04