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[PULL 55/89] target/riscv: Legalize MPP value in write_mstatus
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From: |
Alistair Francis |
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Subject: |
[PULL 55/89] target/riscv: Legalize MPP value in write_mstatus |
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Date: |
Fri, 5 May 2023 11:02:07 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
mstatus.MPP field is a WARL field since priv version 1.11, so we
remain it unchanged if an invalid value is written into it. And
after this, RVH shouldn't be passed to riscv_cpu_set_mode().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 8 ++------
target/riscv/csr.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 29ac7956f7..433ea529b0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -647,12 +647,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env,
uint32_t priv,
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
- if (newpriv > PRV_M) {
- g_assert_not_reached();
- }
- if (newpriv == PRV_RESERVED) {
- newpriv = PRV_U;
- }
+ g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
+
if (icount_enabled() && newpriv != env->priv) {
riscv_itrigger_update_priv(env);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0b871f6dc..f4d2dcfdc8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1230,6 +1230,32 @@ static bool validate_vm(CPURISCVState *env, target_ulong
vm)
satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
}
+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
+ target_ulong val)
+{
+ bool valid = false;
+ target_ulong new_mpp = get_field(val, MSTATUS_MPP);
+
+ switch (new_mpp) {
+ case PRV_M:
+ valid = true;
+ break;
+ case PRV_S:
+ valid = riscv_has_ext(env, RVS);
+ break;
+ case PRV_U:
+ valid = riscv_has_ext(env, RVU);
+ break;
+ }
+
+ /* Remain field unchanged if new_mpp value is invalid */
+ if (!valid) {
+ val = set_field(val, MSTATUS_MPP, old_mpp);
+ }
+
+ return val;
+}
+
static RISCVException write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
@@ -1237,6 +1263,12 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
uint64_t mask = 0;
RISCVMXL xl = riscv_cpu_mxl(env);
+ /*
+ * MPP field have been made WARL since priv version 1.11. However,
+ * legalization for it will not break any software running on 1.10.
+ */
+ val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
+
/* flush tlb on mstatus fields that affect VM */
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
MSTATUS_MPRV | MSTATUS_SUM)) {
--
2.40.0
- [PULL 44/89] target/riscv: remove cpu->cfg.ext_s, (continued)
- [PULL 44/89] target/riscv: remove cpu->cfg.ext_s, Alistair Francis, 2023/05/04
- [PULL 46/89] target/riscv: remove cpu->cfg.ext_h, Alistair Francis, 2023/05/04
- [PULL 48/89] target/riscv: remove cpu->cfg.ext_v, Alistair Francis, 2023/05/04
- [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg(), Alistair Francis, 2023/05/04
- [PULL 47/89] target/riscv: remove cpu->cfg.ext_j, Alistair Francis, 2023/05/04
- [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g, Alistair Francis, 2023/05/04
- [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props(), Alistair Francis, 2023/05/04
- [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Alistair Francis, 2023/05/04
- [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET, Alistair Francis, 2023/05/04
- [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H, Alistair Francis, 2023/05/04
- [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus,
Alistair Francis <=
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx, Alistair Francis, 2023/05/04
- [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags, Alistair Francis, 2023/05/04
- [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Alistair Francis, 2023/05/04
- [PULL 58/89] target/riscv: Extract virt enabled state from tb flags, Alistair Francis, 2023/05/04
- [PULL 57/89] target/riscv: fix H extension TVM trap, Alistair Francis, 2023/05/04
- [PULL 59/89] target/riscv: Add a general status enum for extensions, Alistair Francis, 2023/05/04
- [PULL 62/89] target/riscv: Add a tb flags field for vstart, Alistair Francis, 2023/05/04
- [PULL 63/89] target/riscv: Separate priv from mmu_idx, Alistair Francis, 2023/05/04
- [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX, Alistair Francis, 2023/05/04
- [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Alistair Francis, 2023/05/04