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[PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhin
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From: |
Alistair Francis |
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Subject: |
[PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx |
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Date: |
Fri, 5 May 2023 11:02:08 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done
by check currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230408135908.25269-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d1769fd218..fab38859ec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -916,8 +916,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
cpu->cfg.ext_zhinxmin = true;
}
- if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
- cpu->cfg.ext_zfinx = true;
+ if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
+ error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
+ return;
}
if (cpu->cfg.ext_zfinx) {
--
2.40.0
- [PULL 46/89] target/riscv: remove cpu->cfg.ext_h, (continued)
- [PULL 46/89] target/riscv: remove cpu->cfg.ext_h, Alistair Francis, 2023/05/04
- [PULL 48/89] target/riscv: remove cpu->cfg.ext_v, Alistair Francis, 2023/05/04
- [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg(), Alistair Francis, 2023/05/04
- [PULL 47/89] target/riscv: remove cpu->cfg.ext_j, Alistair Francis, 2023/05/04
- [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g, Alistair Francis, 2023/05/04
- [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props(), Alistair Francis, 2023/05/04
- [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Alistair Francis, 2023/05/04
- [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET, Alistair Francis, 2023/05/04
- [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H, Alistair Francis, 2023/05/04
- [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus, Alistair Francis, 2023/05/04
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx,
Alistair Francis <=
- [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags, Alistair Francis, 2023/05/04
- [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Alistair Francis, 2023/05/04
- [PULL 58/89] target/riscv: Extract virt enabled state from tb flags, Alistair Francis, 2023/05/04
- [PULL 57/89] target/riscv: fix H extension TVM trap, Alistair Francis, 2023/05/04
- [PULL 59/89] target/riscv: Add a general status enum for extensions, Alistair Francis, 2023/05/04
- [PULL 62/89] target/riscv: Add a tb flags field for vstart, Alistair Francis, 2023/05/04
- [PULL 63/89] target/riscv: Separate priv from mmu_idx, Alistair Francis, 2023/05/04
- [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX, Alistair Francis, 2023/05/04
- [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Alistair Francis, 2023/05/04
- [PULL 68/89] target/riscv: Introduce mmuidx_sum, Alistair Francis, 2023/05/04