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[PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX
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From: |
Alistair Francis |
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Subject: |
[PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX |
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Date: |
Fri, 5 May 2023 11:02:17 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
Use the new functions to properly check execute permission
for the read rather than read permission.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 0adfd1ca9a..49179e7a5a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -427,18 +427,27 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
helper_hyp_tlb_flush(env);
}
+/*
+ * TODO: These implementations are not quite correct. They perform the
+ * access using execute permission just fine, but the final PMP check
+ * is supposed to have read permission as well. Without replicating
+ * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx
+ * which would imply that exact check in tlb_fill.
+ */
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
{
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
- return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
+ return cpu_ldw_code_mmu(env, address, oi, GETPC());
}
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
{
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
- return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
+ return cpu_ldl_code_mmu(env, address, oi, GETPC());
}
#endif /* !CONFIG_USER_ONLY */
--
2.40.0
- [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H, (continued)
- [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H, Alistair Francis, 2023/05/04
- [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus, Alistair Francis, 2023/05/04
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx, Alistair Francis, 2023/05/04
- [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags, Alistair Francis, 2023/05/04
- [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Alistair Francis, 2023/05/04
- [PULL 58/89] target/riscv: Extract virt enabled state from tb flags, Alistair Francis, 2023/05/04
- [PULL 57/89] target/riscv: fix H extension TVM trap, Alistair Francis, 2023/05/04
- [PULL 59/89] target/riscv: Add a general status enum for extensions, Alistair Francis, 2023/05/04
- [PULL 62/89] target/riscv: Add a tb flags field for vstart, Alistair Francis, 2023/05/04
- [PULL 63/89] target/riscv: Separate priv from mmu_idx, Alistair Francis, 2023/05/04
- [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX,
Alistair Francis <=
- [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Alistair Francis, 2023/05/04
- [PULL 68/89] target/riscv: Introduce mmuidx_sum, Alistair Francis, 2023/05/04
- [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change, Alistair Francis, 2023/05/04
- [PULL 66/89] target/riscv: Handle HLV, HSV via helpers, Alistair Francis, 2023/05/04
- [PULL 70/89] target/riscv: Introduce mmuidx_2stage, Alistair Francis, 2023/05/04
- [PULL 69/89] target/riscv: Introduce mmuidx_priv, Alistair Francis, 2023/05/04
- [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv, Alistair Francis, 2023/05/04
- [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Alistair Francis, 2023/05/04
- [PULL 74/89] target/riscv: Hoist second stage mode change to callers, Alistair Francis, 2023/05/04
- [PULL 73/89] target/riscv: Check SUM in the correct register, Alistair Francis, 2023/05/04