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[PULL 68/89] target/riscv: Introduce mmuidx_sum
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From: |
Alistair Francis |
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Subject: |
[PULL 68/89] target/riscv: Introduce mmuidx_sum |
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Date: |
Fri, 5 May 2023 11:02:20 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
In get_physical_address, we should use the setting passed
via mmu_idx rather than checking env->mstatus directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 5 +++++
target/riscv/cpu_helper.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 7b63c0f1b6..0b61f337dd 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,11 @@
#define MMUIdx_M 3
#define MMU_2STAGE_BIT (1 << 2)
+static inline bool mmuidx_sum(int mmu_idx)
+{
+ return (mmu_idx & 3) == MMUIdx_S_SUM;
+}
+
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 291a1acbf7..29ee9b1b42 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -842,7 +842,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
widened = 2;
}
/* status.SUM will be ignored if execute on background */
- sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
+ sum = mmuidx_sum(mmu_idx) || use_background || is_debug;
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
--
2.40.0
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx, (continued)
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx, Alistair Francis, 2023/05/04
- [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags, Alistair Francis, 2023/05/04
- [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Alistair Francis, 2023/05/04
- [PULL 58/89] target/riscv: Extract virt enabled state from tb flags, Alistair Francis, 2023/05/04
- [PULL 57/89] target/riscv: fix H extension TVM trap, Alistair Francis, 2023/05/04
- [PULL 59/89] target/riscv: Add a general status enum for extensions, Alistair Francis, 2023/05/04
- [PULL 62/89] target/riscv: Add a tb flags field for vstart, Alistair Francis, 2023/05/04
- [PULL 63/89] target/riscv: Separate priv from mmu_idx, Alistair Francis, 2023/05/04
- [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX, Alistair Francis, 2023/05/04
- [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Alistair Francis, 2023/05/04
- [PULL 68/89] target/riscv: Introduce mmuidx_sum,
Alistair Francis <=
- [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change, Alistair Francis, 2023/05/04
- [PULL 66/89] target/riscv: Handle HLV, HSV via helpers, Alistair Francis, 2023/05/04
- [PULL 70/89] target/riscv: Introduce mmuidx_2stage, Alistair Francis, 2023/05/04
- [PULL 69/89] target/riscv: Introduce mmuidx_priv, Alistair Francis, 2023/05/04
- [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv, Alistair Francis, 2023/05/04
- [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Alistair Francis, 2023/05/04
- [PULL 74/89] target/riscv: Hoist second stage mode change to callers, Alistair Francis, 2023/05/04
- [PULL 73/89] target/riscv: Check SUM in the correct register, Alistair Francis, 2023/05/04
- [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop, Alistair Francis, 2023/05/04
- [PULL 77/89] target/riscv: Suppress pte update with is_debug, Alistair Francis, 2023/05/04