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[PULL 79/89] target/riscv: Merge checks for reserved pte flags
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From: |
Alistair Francis |
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Subject: |
[PULL 79/89] target/riscv: Merge checks for reserved pte flags |
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Date: |
Fri, 5 May 2023 11:02:31 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9a2b944990..c7c384bae3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -962,14 +962,14 @@ restart:
/* Reserved without Svpbmt. */
return TRANSLATE_FAIL;
}
- if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
- /* Reserved leaf PTE flags: PTE_W */
- return TRANSLATE_FAIL;
- }
- if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
- /* Reserved leaf PTE flags: PTE_W + PTE_X */
+
+ /* Check for reserved combinations of RWX flags. */
+ switch (pte & (PTE_R | PTE_W | PTE_X)) {
+ case PTE_W:
+ case PTE_W | PTE_X:
return TRANSLATE_FAIL;
}
+
if ((pte & PTE_U) &&
((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
/*
--
2.40.0
- [PULL 69/89] target/riscv: Introduce mmuidx_priv, (continued)
- [PULL 69/89] target/riscv: Introduce mmuidx_priv, Alistair Francis, 2023/05/04
- [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv, Alistair Francis, 2023/05/04
- [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Alistair Francis, 2023/05/04
- [PULL 74/89] target/riscv: Hoist second stage mode change to callers, Alistair Francis, 2023/05/04
- [PULL 73/89] target/riscv: Check SUM in the correct register, Alistair Francis, 2023/05/04
- [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop, Alistair Francis, 2023/05/04
- [PULL 77/89] target/riscv: Suppress pte update with is_debug, Alistair Francis, 2023/05/04
- [PULL 76/89] target/riscv: Move leaf pte processing out of level loop, Alistair Francis, 2023/05/04
- [PULL 78/89] target/riscv: Don't modify SUM with is_debug, Alistair Francis, 2023/05/04
- [PULL 81/89] target/riscv: Reorg sum check in get_physical_address, Alistair Francis, 2023/05/04
- [PULL 79/89] target/riscv: Merge checks for reserved pte flags,
Alistair Francis <=
- [PULL 80/89] target/riscv: Reorg access check in get_physical_address, Alistair Francis, 2023/05/04
- [PULL 83/89] target/riscv: add CPU QOM header, Alistair Francis, 2023/05/04
- [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior, Alistair Francis, 2023/05/04
- [PULL 84/89] target/riscv: add query-cpy-definitions support, Alistair Francis, 2023/05/04
- [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU, Alistair Francis, 2023/05/04
- [PULL 87/89] target/riscv: Fix Guest Physical Address Translation, Alistair Francis, 2023/05/04
- [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU, Alistair Francis, 2023/05/04
- [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state, Alistair Francis, 2023/05/04