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[PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state
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From: |
Alistair Francis |
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Subject: |
[PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state |
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Date: |
Fri, 5 May 2023 11:02:34 +1000 |
From: Ivan Klokov <ivan.klokov@syntacore.com>
Since g_new is used to initialize the RISCVAPLICState->state structure,
in some case we get behavior that is not as expected. This patch
changes this to g_new0, which allows to initialize the APLIC in the correct
state.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <20230413133432.53771-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aplic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index cd7efc4ad4..afc5b54dbb 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -803,7 +803,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error
**errp)
aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
- aplic->state = g_new(uint32_t, aplic->num_irqs);
+ aplic->state = g_new0(uint32_t, aplic->num_irqs);
aplic->target = g_new0(uint32_t, aplic->num_irqs);
if (!aplic->msimode) {
for (i = 0; i < aplic->num_irqs; i++) {
--
2.40.0
- [PULL 79/89] target/riscv: Merge checks for reserved pte flags, (continued)
- [PULL 79/89] target/riscv: Merge checks for reserved pte flags, Alistair Francis, 2023/05/04
- [PULL 80/89] target/riscv: Reorg access check in get_physical_address, Alistair Francis, 2023/05/04
- [PULL 83/89] target/riscv: add CPU QOM header, Alistair Francis, 2023/05/04
- [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior, Alistair Francis, 2023/05/04
- [PULL 84/89] target/riscv: add query-cpy-definitions support, Alistair Francis, 2023/05/04
- [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU, Alistair Francis, 2023/05/04
- [PULL 87/89] target/riscv: Fix Guest Physical Address Translation, Alistair Francis, 2023/05/04
- [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU, Alistair Francis, 2023/05/04
- [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state,
Alistair Francis <=
- [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed, Alistair Francis, 2023/05/04
- Re: [PULL 00/89] riscv-to-apply queue, Richard Henderson, 2023/05/05