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[PULL 17/42] target/sparc: Use cpu_ld*_code_mmu
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From: |
Richard Henderson |
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Subject: |
[PULL 17/42] target/sparc: Use cpu_ld*_code_mmu |
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Date: |
Fri, 5 May 2023 22:24:22 +0100 |
This passes on the memop as given as argument to
helper_ld_asi to the ultimate load primitive.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/ldst_helper.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index a53580d9e4..7972d56a72 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -593,6 +593,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong
addr,
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
uint32_t last_addr = addr;
#endif
+ MemOpIdx oi;
do_check_align(env, addr, size - 1, GETPC());
switch (asi) {
@@ -692,19 +693,20 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong
addr,
case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
break;
case ASI_KERNELTXT: /* Supervisor code access */
+ oi = make_memop_idx(memop, cpu_mmu_index(env, true));
switch (size) {
case 1:
- ret = cpu_ldub_code(env, addr);
+ ret = cpu_ldb_code_mmu(env, addr, oi, GETPC());
break;
case 2:
- ret = cpu_lduw_code(env, addr);
+ ret = cpu_ldw_code_mmu(env, addr, oi, GETPC());
break;
default:
case 4:
- ret = cpu_ldl_code(env, addr);
+ ret = cpu_ldl_code_mmu(env, addr, oi, GETPC());
break;
case 8:
- ret = cpu_ldq_code(env, addr);
+ ret = cpu_ldq_code_mmu(env, addr, oi, GETPC());
break;
}
break;
--
2.34.1
- [PULL 07/42] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*, (continued)
- [PULL 07/42] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*, Richard Henderson, 2023/05/05
- [PULL 16/42] target/sparc: Use MO_ALIGN where required, Richard Henderson, 2023/05/05
- [PULL 15/42] target/hppa: Remove TARGET_ALIGNED_ONLY, Richard Henderson, 2023/05/05
- [PULL 11/42] target/alpha: Use MO_ALIGN for system UNALIGN(), Richard Henderson, 2023/05/05
- [PULL 08/42] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*, Richard Henderson, 2023/05/05
- [PULL 09/42] target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*, Richard Henderson, 2023/05/05
- [PULL 13/42] target/alpha: Remove TARGET_ALIGNED_ONLY, Richard Henderson, 2023/05/05
- [PULL 18/42] target/sparc: Remove TARGET_ALIGNED_ONLY, Richard Henderson, 2023/05/05
- [PULL 10/42] tcg: Remove compatability helpers for qemu ld/st, Richard Henderson, 2023/05/05
- [PULL 12/42] target/alpha: Use MO_ALIGN where required, Richard Henderson, 2023/05/05
- [PULL 17/42] target/sparc: Use cpu_ld*_code_mmu,
Richard Henderson <=
- [PULL 21/42] tcg/i386: Introduce HostAddress, Richard Henderson, 2023/05/05
- [PULL 25/42] tcg/aarch64: Introduce HostAddress, Richard Henderson, 2023/05/05
- [PULL 22/42] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load, Richard Henderson, 2023/05/05
- [PULL 28/42] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st}, Richard Henderson, 2023/05/05
- [PULL 31/42] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 24/42] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 26/42] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 29/42] tcg/loongarch64: Introduce HostAddress, Richard Henderson, 2023/05/05
- [PULL 30/42] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 32/42] tcg/ppc: Introduce HostAddress, Richard Henderson, 2023/05/05