[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 23/42] tcg/i386: Introduce tcg_out_testi
|
From: |
Richard Henderson |
|
Subject: |
[PULL 23/42] tcg/i386: Introduce tcg_out_testi |
|
Date: |
Fri, 5 May 2023 22:24:28 +0100 |
Split out a helper for choosing testb vs testl.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 30 ++++++++++++++++++------------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 78160f453b..aae698121a 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1751,6 +1751,23 @@ static void tcg_out_nopn(TCGContext *s, int n)
tcg_out8(s, 0x90);
}
+/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */
+static void __attribute__((unused))
+tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i)
+{
+ /*
+ * This is used for testing alignment, so we can usually use testb.
+ * For i686, we have to use testl for %esi/%edi.
+ */
+ if (i <= 0xff && (TCG_TARGET_REG_BITS == 64 || r < 4)) {
+ tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r);
+ tcg_out8(s, i);
+ } else {
+ tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r);
+ tcg_out32(s, i);
+ }
+}
+
typedef struct {
TCGReg base;
int index;
@@ -2051,18 +2068,7 @@ static void tcg_out_test_alignment(TCGContext *s, bool
is_ld, TCGReg addrlo,
unsigned a_mask = (1 << a_bits) - 1;
TCGLabelQemuLdst *label;
- /*
- * We are expecting a_bits to max out at 7, so we can usually use testb.
- * For i686, we have to use testl for %esi/%edi.
- */
- if (a_mask <= 0xff && (TCG_TARGET_REG_BITS == 64 || addrlo < 4)) {
- tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, addrlo);
- tcg_out8(s, a_mask);
- } else {
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo);
- tcg_out32(s, a_mask);
- }
-
+ tcg_out_testi(s, addrlo, a_mask);
/* jne slow_path */
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
--
2.34.1
- [PULL 32/42] tcg/ppc: Introduce HostAddress, (continued)
- [PULL 32/42] tcg/ppc: Introduce HostAddress, Richard Henderson, 2023/05/05
- [PULL 27/42] tcg/arm: Introduce HostAddress, Richard Henderson, 2023/05/05
- [PULL 19/42] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 20/42] tcg/i386: Generalize multi-part load overlap test, Richard Henderson, 2023/05/05
- [PULL 34/42] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 35/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 38/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/05/05
- [PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64, Richard Henderson, 2023/05/05
- [PULL 39/42] tcg: Move TCGLabelQemuLdst to tcg.c, Richard Henderson, 2023/05/05
- [PULL 36/42] tcg/s390x: Introduce HostAddress, Richard Henderson, 2023/05/05
- [PULL 23/42] tcg/i386: Introduce tcg_out_testi,
Richard Henderson <=
- [PULL 37/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return, Richard Henderson, 2023/05/05
- [PULL 40/42] tcg: Replace REG_P with arg_loc_reg_p, Richard Henderson, 2023/05/05
- [PULL 41/42] tcg: Introduce arg_slot_stk_ofs, Richard Henderson, 2023/05/05
- [PULL 42/42] tcg: Widen helper_*_st[bw]_mmu val arguments, Richard Henderson, 2023/05/05
- Re: [PULL 00/42] tcg patch queue, Richard Henderson, 2023/05/06