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Re: [PULL 86/89] target/riscv: Restore the predicate() NULL check behavi
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From: |
Alistair Francis |
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Subject: |
Re: [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior |
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Date: |
Mon, 8 May 2023 08:21:17 +1000 |
On Fri, May 5, 2023 at 11:08 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> From: Bin Meng <bmeng@tinylab.org>
>
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
> Some comments are also added to indicate that predicate() must be
> provided for an implemented CSR.
>
> Reported-by: Fei Wu <fei2.wu@intel.com>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Sorry, I didn't realise I should have done this with the PR, but this
is a good candidate for going into 8.0.1
Alistair
> ---
> target/riscv/csr.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 865ee9efda..4451bd1263 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3826,6 +3826,11 @@ static inline RISCVException
> riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /* ensure CSR is implemented by checking predicate */
> + if (!csr_ops[csrno].predicate) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> /* privileged spec version check */
> if (env->priv_ver < csr_min_priv) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -3843,7 +3848,6 @@ static inline RISCVException
> riscv_csrrw_check(CPURISCVState *env,
> * illegal instruction exception should be triggered instead of virtual
> * instruction exception. Hence this comes after the read / write check.
> */
> - g_assert(csr_ops[csrno].predicate != NULL);
> RISCVException ret = csr_ops[csrno].predicate(env, csrno);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
> @@ -4032,7 +4036,10 @@ static RISCVException write_jvt(CPURISCVState *env,
> int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -/* Control and Status Register function table */
> +/*
> + * Control and Status Register function table
> + * riscv_csr_operations::predicate() must be provided for an implemented CSR
> + */
> riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* User Floating-Point CSRs */
> [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
> --
> 2.40.0
>
- [PULL 73/89] target/riscv: Check SUM in the correct register, (continued)
- [PULL 73/89] target/riscv: Check SUM in the correct register, Alistair Francis, 2023/05/04
- [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop, Alistair Francis, 2023/05/04
- [PULL 77/89] target/riscv: Suppress pte update with is_debug, Alistair Francis, 2023/05/04
- [PULL 76/89] target/riscv: Move leaf pte processing out of level loop, Alistair Francis, 2023/05/04
- [PULL 78/89] target/riscv: Don't modify SUM with is_debug, Alistair Francis, 2023/05/04
- [PULL 81/89] target/riscv: Reorg sum check in get_physical_address, Alistair Francis, 2023/05/04
- [PULL 79/89] target/riscv: Merge checks for reserved pte flags, Alistair Francis, 2023/05/04
- [PULL 80/89] target/riscv: Reorg access check in get_physical_address, Alistair Francis, 2023/05/04
- [PULL 83/89] target/riscv: add CPU QOM header, Alistair Francis, 2023/05/04
- [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior, Alistair Francis, 2023/05/04
- Re: [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior,
Alistair Francis <=
- [PULL 84/89] target/riscv: add query-cpy-definitions support, Alistair Francis, 2023/05/04
- [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU, Alistair Francis, 2023/05/04
- [PULL 87/89] target/riscv: Fix Guest Physical Address Translation, Alistair Francis, 2023/05/04
- [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU, Alistair Francis, 2023/05/04
- [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state, Alistair Francis, 2023/05/04
- [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed, Alistair Francis, 2023/05/04
- Re: [PULL 00/89] riscv-to-apply queue, Richard Henderson, 2023/05/05