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[PATCH v5 13/54] tcg/aarch64: Detect have_lse, have_lse2 for darwin
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From: |
Richard Henderson |
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Subject: |
[PATCH v5 13/54] tcg/aarch64: Detect have_lse, have_lse2 for darwin |
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Date: |
Mon, 15 May 2023 07:32:32 -0700 |
These features are present for Apple M1.
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index fc551a3d10..c64606af5b 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -16,6 +16,9 @@
#ifdef __linux__
#include <asm/hwcap.h>
#endif
+#ifdef CONFIG_DARWIN
+#include <sys/sysctl.h>
+#endif
/* We're going to re-use TCGType in setting of the SF bit, which controls
the size of the operation performed. If we know the values match, it
@@ -2903,6 +2906,27 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
}
}
+#ifdef CONFIG_DARWIN
+static bool sysctl_for_bool(const char *name)
+{
+ int val = 0;
+ size_t len = sizeof(val);
+
+ if (sysctlbyname(name, &val, &len, NULL, 0) == 0) {
+ return val != 0;
+ }
+
+ /*
+ * We might in the future ask for properties not present in older kernels,
+ * but we're only asking about static properties, all of which should be
+ * 'int'. So we shouln't see ENOMEM (val too small), or any of the other
+ * more exotic errors.
+ */
+ assert(errno == ENOENT);
+ return false;
+}
+#endif
+
static void tcg_target_init(TCGContext *s)
{
#ifdef __linux__
@@ -2910,6 +2934,10 @@ static void tcg_target_init(TCGContext *s)
have_lse = hwcap & HWCAP_ATOMICS;
have_lse2 = hwcap & HWCAP_USCAT;
#endif
+#ifdef CONFIG_DARWIN
+ have_lse = sysctl_for_bool("hw.optional.arm.FEAT_LSE");
+ have_lse2 = sysctl_for_bool("hw.optional.arm.FEAT_LSE2");
+#endif
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
--
2.34.1
- [PATCH v5 20/54] tcg/arm: Adjust constraints on qemu_ld/st, (continued)
- [PATCH v5 20/54] tcg/arm: Adjust constraints on qemu_ld/st, Richard Henderson, 2023/05/15
- [PATCH v5 17/54] tcg/ppc: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 16/54] tcg/aarch64: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 22/54] tcg/mips: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 39/54] tcg: Introduce atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 23/54] tcg/s390x: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 15/54] tcg/i386: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 18/54] tcg/loongarch64: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15
- [PATCH v5 13/54] tcg/aarch64: Detect have_lse, have_lse2 for darwin,
Richard Henderson <=
- [PATCH v5 38/54] tcg: Support TCG_TYPE_I128 in tcg_out_{ld, st}_helper_{args, ret}, Richard Henderson, 2023/05/15
- [PATCH v5 36/54] tcg: Introduce tcg_out_movext3, Richard Henderson, 2023/05/15
- [PATCH v5 35/54] tcg: Add INDEX_op_qemu_{ld,st}_i128, Richard Henderson, 2023/05/15
- [PATCH v5 31/54] tcg/loongarch64: Check the host supports unaligned accesses, Richard Henderson, 2023/05/15
- [PATCH v5 28/54] tcg/sparc64: Split out tcg_out_movi_s32, Richard Henderson, 2023/05/15
- [PATCH v5 26/54] target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32, Richard Henderson, 2023/05/15