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[PULL 42/80] tcg/mips: Use atom_and_align_for_opc
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From: |
Richard Henderson |
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Subject: |
[PULL 42/80] tcg/mips: Use atom_and_align_for_opc |
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Date: |
Tue, 16 May 2023 12:41:07 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index cd0254a0d7..3f3fe5b991 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1138,7 +1138,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *l)
typedef struct {
TCGReg base;
- MemOp align;
+ TCGAtomAlign aa;
} HostAddress;
bool tcg_target_has_memory_bswap(MemOp memop)
@@ -1158,11 +1158,15 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext
*s, HostAddress *h,
{
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
- unsigned a_bits = get_alignment_bits(opc);
+ MemOp a_bits;
unsigned s_bits = opc & MO_SIZE;
- unsigned a_mask = (1 << a_bits) - 1;
+ unsigned a_mask;
TCGReg base;
+ h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
+ a_bits = h->aa.align;
+ a_mask = (1 << a_bits) - 1;
+
#ifdef CONFIG_SOFTMMU
unsigned s_mask = (1 << s_bits) - 1;
int mem_index = get_mmuidx(oi);
@@ -1281,7 +1285,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
#endif
h->base = base;
- h->align = a_bits;
return ldst;
}
@@ -1394,7 +1397,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo,
TCGReg datahi,
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
- if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
+ if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
} else {
tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type);
@@ -1481,7 +1484,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo,
TCGReg datahi,
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
- if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
+ if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
} else {
tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
--
2.34.1
- [PULL 32/80] tcg: Introduce tcg_target_has_memory_bswap, (continued)
- [PULL 32/80] tcg: Introduce tcg_target_has_memory_bswap, Richard Henderson, 2023/05/16
- [PULL 34/80] tcg: Introduce tcg_out_movext3, Richard Henderson, 2023/05/16
- [PULL 35/80] tcg: Merge tcg_out_helper_load_regs into caller, Richard Henderson, 2023/05/16
- [PULL 37/80] tcg: Introduce atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 33/80] tcg: Add INDEX_op_qemu_{ld,st}_i128, Richard Henderson, 2023/05/16
- [PULL 36/80] tcg: Support TCG_TYPE_I128 in tcg_out_{ld, st}_helper_{args, ret}, Richard Henderson, 2023/05/16
- [PULL 39/80] tcg/aarch64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 38/80] tcg/i386: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 40/80] tcg/arm: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 41/80] tcg/loongarch64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 42/80] tcg/mips: Use atom_and_align_for_opc,
Richard Henderson <=
- [PULL 44/80] tcg/riscv: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 46/80] tcg/sparc64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 45/80] tcg/s390x: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 47/80] tcg/i386: Honor 64-bit atomicity in 32-bit mode, Richard Henderson, 2023/05/16
- [PULL 52/80] tcg/s390x: Support 128-bit load/store, Richard Henderson, 2023/05/16
- [PULL 65/80] tcg: Remove TCGv from tcg_gen_atomic_*, Richard Henderson, 2023/05/16
- [PULL 64/80] tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*, Richard Henderson, 2023/05/16
- [PULL 68/80] tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32, Richard Henderson, 2023/05/16
- [PULL 74/80] tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/16
- [PULL 56/80] tcg: Widen helper_{ld,st}_i128 addresses to uint64_t, Richard Henderson, 2023/05/16