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[PULL 70/80] tcg/i386: Adjust type of tlb_mask
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From: |
Richard Henderson |
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Subject: |
[PULL 70/80] tcg/i386: Adjust type of tlb_mask |
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Date: |
Tue, 16 May 2023 12:41:35 -0700 |
Because of its use on tgen_arithi, this value must be a signed
32-bit quantity, as that is what may be encoded in the insn.
The truncation of the value to unsigned for 32-bit guests is
done via the REX bit via 'trexw'.
Removes the only uses of target_ulong from this tcg backend.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index aed5bbd94c..653e3e10a8 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1966,7 +1966,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
int trexw = 0, hrexw = 0, tlbrexw = 0;
unsigned mem_index = get_mmuidx(oi);
unsigned s_mask = (1 << s_bits) - 1;
- target_ulong tlb_mask;
+ int tlb_mask;
ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
@@ -2011,7 +2011,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
HostAddress *h,
tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
addrlo, s_mask - a_mask);
}
- tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
+ tlb_mask = TARGET_PAGE_MASK | a_mask;
tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
/* cmp 0(TCG_REG_L0), TCG_REG_L1 */
--
2.34.1
- [PULL 43/80] tcg/ppc: Use atom_and_align_for_opc, (continued)
- [PULL 43/80] tcg/ppc: Use atom_and_align_for_opc, Richard Henderson, 2023/05/16
- [PULL 48/80] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2023/05/16
- [PULL 50/80] tcg/aarch64: Support 128-bit load/store, Richard Henderson, 2023/05/16
- [PULL 58/80] tcg: Widen tcg_gen_code pc_start argument to uint64_t, Richard Henderson, 2023/05/16
- [PULL 49/80] tcg/aarch64: Rename temporaries, Richard Henderson, 2023/05/16
- [PULL 51/80] tcg/ppc: Support 128-bit load/store, Richard Henderson, 2023/05/16
- [PULL 55/80] accel/tcg: Widen tcg-ldst.h addresses to uint64_t, Richard Henderson, 2023/05/16
- [PULL 54/80] tcg: Widen gen_insn_data to uint64_t, Richard Henderson, 2023/05/16
- [PULL 57/80] tcg: Widen helper_atomic_* addresses to uint64_t, Richard Henderson, 2023/05/16
- [PULL 59/80] accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback, Richard Henderson, 2023/05/16
- [PULL 70/80] tcg/i386: Adjust type of tlb_mask,
Richard Henderson <=
- [PULL 53/80] tcg: Split out memory ops to tcg-op-ldst.c, Richard Henderson, 2023/05/16
- [PULL 63/80] tcg: Add addr_type to TCGContext, Richard Henderson, 2023/05/16
- [PULL 66/80] tcg: Split INDEX_op_qemu_{ld, st}* for guest address size, Richard Henderson, 2023/05/16
- [PULL 72/80] tcg/arm: Remove TARGET_LONG_BITS, Richard Henderson, 2023/05/16
- [PULL 73/80] tcg/aarch64: Remove USE_GUEST_BASE, Richard Henderson, 2023/05/16
- [PULL 76/80] tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/16
- [PULL 67/80] tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong, Richard Henderson, 2023/05/16
- [PULL 78/80] tcg: Add page_bits and page_mask to TCGContext, Richard Henderson, 2023/05/16
- [PULL 77/80] tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/16
- [PULL 60/80] accel/tcg: Merge do_gen_mem_cb into caller, Richard Henderson, 2023/05/16