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Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb |
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Date: |
Wed, 17 May 2023 09:40:00 +1000 |
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
> 1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index c5b060023f..53a7f97b29 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -593,26 +593,42 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret,
> TCGReg arg)
>
> static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
> {
> - tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> - tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
> + if (have_zbb) {
> + tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
> + } else {
> + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> + tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
> + }
> }
>
> static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
> {
> - tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
> - tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
> + if (have_zba) {
> + tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
> + } else {
> + tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
> + tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
> + }
> }
>
> static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg
> arg)
> {
> - tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
> - tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
> + if (have_zbb) {
> + tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
> + } else {
> + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
> + tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
> + }
> }
>
> static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg
> arg)
> {
> - tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> - tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
> + if (have_zbb) {
> + tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
> + } else {
> + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> + tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
> + }
> }
>
> static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
> --
> 2.34.1
>
>
- Re: [PATCH 06/11] tcg/riscv: Support rotates from Zbb, (continued)
- [PATCH 01/11] disas/riscv: Decode czero.{eqz,nez}, Richard Henderson, 2023/05/03
- [PATCH 02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/03
- [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Richard Henderson, 2023/05/03
- [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation, Richard Henderson, 2023/05/03
- [PATCH 07/11] tcg/riscv: Support REV8 from Zbb, Richard Henderson, 2023/05/03
- [PATCH 09/11] tcg/riscv: Improve setcond expansion, Richard Henderson, 2023/05/03
- [PATCH 10/11] tcg/riscv: Implement movcond, Richard Henderson, 2023/05/03