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[PULL 05/40] docs/cxl: Remove incorrect CXL type 3 size parameter
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From: |
Michael S. Tsirkin |
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Subject: |
[PULL 05/40] docs/cxl: Remove incorrect CXL type 3 size parameter |
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Date: |
Fri, 19 May 2023 10:49:57 -0400 |
From: Raghu H <raghuhack78@gmail.com>
cxl-type3 memory size is read directly from the provided memory backed end
device. Remove non existent size option
Signed-off-by: Raghu H <raghuhack78@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230421134507.26842-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
docs/system/devices/cxl.rst | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 9618becdab..dd1a62bd57 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -354,13 +354,13 @@ An example of 4 devices below a switch suitable for 1, 2
or 4 way interleave::
-device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \
-device cxl-upstream,bus=root_port0,id=us0 \
-device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \
- -device
cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,size=256M \
+ -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \
-device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \
- -device
cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,size=256M \
+ -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \
-device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \
- -device
cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,size=256M \
+ -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \
-device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \
- -device
cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,size=256M \
+ -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \
-M
cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k
Kernel Configuration Options
--
MST
- [PULL 00/40] virtio,pc,pci: fixes, features, cleanups, Michael S. Tsirkin, 2023/05/19
- [PULL 01/40] vhost: fix possible wrap in SVQ descriptor ring, Michael S. Tsirkin, 2023/05/19
- [PULL 02/40] hw/cxl: cdat: Fix open file not closed in ct3_load_cdat(), Michael S. Tsirkin, 2023/05/19
- [PULL 03/40] hw/cxl: cdat: Fix failure to free buffer in erorr paths, Michael S. Tsirkin, 2023/05/19
- [PULL 04/40] docs/cxl: fix some typos, Michael S. Tsirkin, 2023/05/19
- [PULL 06/40] docs/cxl: Replace unsupported AARCH64 with x86_64, Michael S. Tsirkin, 2023/05/19
- [PULL 05/40] docs/cxl: Remove incorrect CXL type 3 size parameter,
Michael S. Tsirkin <=
- [PULL 07/40] hw/cxl: drop pointless memory_region_transaction_guards, Michael S. Tsirkin, 2023/05/19
- [PULL 08/40] hw/cxl: Fix endian handling for decoder commit., Michael S. Tsirkin, 2023/05/19
- [PULL 09/40] hw/cxl: Fix incorrect reset of commit and associated clearing of committed., Michael S. Tsirkin, 2023/05/19
- [PULL 11/40] hw/mem: Use memory_region_size() in cxl_type3, Michael S. Tsirkin, 2023/05/19
- [PULL 10/40] tests/qtest/cxl-test: whitespace, line ending cleanup, Michael S. Tsirkin, 2023/05/19
- [PULL 13/40] ACPI: bios-tables-test.c step 2 (allowed-diff entries), Michael S. Tsirkin, 2023/05/19
- [PULL 14/40] ACPI: i386: bump to MADT to revision 3, Michael S. Tsirkin, 2023/05/19
- [PULL 12/40] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent), Michael S. Tsirkin, 2023/05/19
- [PULL 17/40] pci: pci_add_option_rom(): refactor: use g_autofree for path variable, Michael S. Tsirkin, 2023/05/19
- [PULL 16/40] pci: pci_add_option_rom(): improve style, Michael S. Tsirkin, 2023/05/19