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[PULL 09/40] hw/cxl: Fix incorrect reset of commit and associated cleari
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From: |
Michael S. Tsirkin |
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Subject: |
[PULL 09/40] hw/cxl: Fix incorrect reset of commit and associated clearing of committed. |
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Date: |
Fri, 19 May 2023 10:50:18 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Tested-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
--
v2: Picked up tags.
Message-Id: <20230421135906.3515-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/cxl/cxl-component-utils.c | 6 +++++-
hw/mem/cxl_type3.c | 21 ++++++++++++++++++++-
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index a3e6cf75cf..378f1082ce 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -38,19 +38,23 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate,
hwaddr offset,
ComponentRegisters *cregs = &cxl_cstate->crb;
uint32_t *cache_mem = cregs->cache_mem_registers;
bool should_commit = false;
+ bool should_uncommit = false;
switch (offset) {
case A_CXL_HDM_DECODER0_CTRL:
should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
+ should_uncommit = !should_commit;
break;
default:
break;
}
if (should_commit) {
- value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
+ } else if (should_uncommit) {
+ value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
+ value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);
}
stl_le_p((uint8_t *)cache_mem + offset, value);
}
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index a2a9b17dbb..1bd5963a3f 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -320,13 +320,28 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int
which)
ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL);
/* TODO: Sanity checks that the decoder is possible */
- ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0);
ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL, ctrl);
}
+static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int which)
+{
+ ComponentRegisters *cregs = &ct3d->cxl_cstate.crb;
+ uint32_t *cache_mem = cregs->cache_mem_registers;
+ uint32_t ctrl;
+
+ assert(which == 0);
+
+ ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL);
+
+ ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0);
+ ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);
+
+ stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL, ctrl);
+}
+
static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
{
switch (qmp_err) {
@@ -395,6 +410,7 @@ static void ct3d_reg_write(void *opaque, hwaddr offset,
uint64_t value,
CXLType3Dev *ct3d = container_of(cxl_cstate, CXLType3Dev, cxl_cstate);
uint32_t *cache_mem = cregs->cache_mem_registers;
bool should_commit = false;
+ bool should_uncommit = false;
int which_hdm = -1;
assert(size == 4);
@@ -403,6 +419,7 @@ static void ct3d_reg_write(void *opaque, hwaddr offset,
uint64_t value,
switch (offset) {
case A_CXL_HDM_DECODER0_CTRL:
should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
+ should_uncommit = !should_commit;
which_hdm = 0;
break;
case A_CXL_RAS_UNC_ERR_STATUS:
@@ -489,6 +506,8 @@ static void ct3d_reg_write(void *opaque, hwaddr offset,
uint64_t value,
stl_le_p((uint8_t *)cache_mem + offset, value);
if (should_commit) {
hdm_decoder_commit(ct3d, which_hdm);
+ } else if (should_uncommit) {
+ hdm_decoder_uncommit(ct3d, which_hdm);
}
}
--
MST
- [PULL 00/40] virtio,pc,pci: fixes, features, cleanups, Michael S. Tsirkin, 2023/05/19
- [PULL 01/40] vhost: fix possible wrap in SVQ descriptor ring, Michael S. Tsirkin, 2023/05/19
- [PULL 02/40] hw/cxl: cdat: Fix open file not closed in ct3_load_cdat(), Michael S. Tsirkin, 2023/05/19
- [PULL 03/40] hw/cxl: cdat: Fix failure to free buffer in erorr paths, Michael S. Tsirkin, 2023/05/19
- [PULL 04/40] docs/cxl: fix some typos, Michael S. Tsirkin, 2023/05/19
- [PULL 06/40] docs/cxl: Replace unsupported AARCH64 with x86_64, Michael S. Tsirkin, 2023/05/19
- [PULL 05/40] docs/cxl: Remove incorrect CXL type 3 size parameter, Michael S. Tsirkin, 2023/05/19
- [PULL 07/40] hw/cxl: drop pointless memory_region_transaction_guards, Michael S. Tsirkin, 2023/05/19
- [PULL 08/40] hw/cxl: Fix endian handling for decoder commit., Michael S. Tsirkin, 2023/05/19
- [PULL 09/40] hw/cxl: Fix incorrect reset of commit and associated clearing of committed.,
Michael S. Tsirkin <=
- [PULL 11/40] hw/mem: Use memory_region_size() in cxl_type3, Michael S. Tsirkin, 2023/05/19
- [PULL 10/40] tests/qtest/cxl-test: whitespace, line ending cleanup, Michael S. Tsirkin, 2023/05/19
- [PULL 13/40] ACPI: bios-tables-test.c step 2 (allowed-diff entries), Michael S. Tsirkin, 2023/05/19
- [PULL 14/40] ACPI: i386: bump to MADT to revision 3, Michael S. Tsirkin, 2023/05/19
- [PULL 12/40] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent), Michael S. Tsirkin, 2023/05/19
- [PULL 17/40] pci: pci_add_option_rom(): refactor: use g_autofree for path variable, Michael S. Tsirkin, 2023/05/19
- [PULL 16/40] pci: pci_add_option_rom(): improve style, Michael S. Tsirkin, 2023/05/19
- [PULL 18/40] vhost-user: send SET_STATUS 0 after GET_VRING_BASE, Michael S. Tsirkin, 2023/05/19
- [PULL 19/40] hw/pci: Disable PCI_ERR_UNCOR_MASK register for machine type < 8.0, Michael S. Tsirkin, 2023/05/19
- [PULL 20/40] virtio-mem: Default to "unplugged-inaccessible=on" with 8.1 on x86-64, Michael S. Tsirkin, 2023/05/19