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[PATCH v2 02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL |
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Date: |
Tue, 23 May 2023 06:52:32 -0700 |
All uses replaced with TCGContext.addr_type.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index ff6334980f..45bd09cfc4 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -908,6 +908,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
TCGReg addr_reg, MemOpIdx oi,
bool is_ld)
{
+ TCGType addr_type = s->addr_type;
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
TCGAtomAlign aa;
@@ -949,19 +950,19 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
addr_adj = addr_reg;
if (a_mask < s_mask) {
addr_adj = TCG_REG_TMP0;
- tcg_out_opc_imm(s, TARGET_LONG_BITS == 32 ? OPC_ADDIW : OPC_ADDI,
+ tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI,
addr_adj, addr_reg, s_mask - a_mask);
}
compare_mask = s->page_mask | a_mask;
if (compare_mask == sextreg(compare_mask, 0, 12)) {
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask);
} else {
- tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
+ tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask);
tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj);
}
/* Load the tlb comparator and the addend. */
- tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
+ tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
is_ld ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
@@ -973,7 +974,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
/* TLB Hit - translate address using addend. */
addr_adj = addr_reg;
- if (TARGET_LONG_BITS == 32) {
+ if (addr_type == TCG_TYPE_I32) {
addr_adj = TCG_REG_TMP0;
tcg_out_ext32u(s, addr_adj, addr_reg);
}
@@ -995,7 +996,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s,
TCGReg *pbase,
}
TCGReg base = addr_reg;
- if (TARGET_LONG_BITS == 32) {
+ if (addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_REG_TMP0, base);
base = TCG_REG_TMP0;
}
--
2.34.1
- [PATCH v2 00/52] tcg: Build once for system, once for user, Richard Henderson, 2023/05/23
- [PATCH v2 01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/23
- [PATCH v2 03/52] tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/23
- [PATCH v2 05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h, Richard Henderson, 2023/05/23
- [PATCH v2 04/52] tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/05/23
- [PATCH v2 08/52] tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS, Richard Henderson, 2023/05/23
- [PATCH v2 02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL,
Richard Henderson <=
- [PATCH v2 12/52] tcg: Split out tcg-target-reg-bits.h, Richard Henderson, 2023/05/23
- [PATCH v2 06/52] tcg: Widen CPUTLBEntry comparators to 64-bits, Richard Henderson, 2023/05/23
- [PATCH v2 11/52] *: Add missing includes of tcg/tcg.h, Richard Henderson, 2023/05/23
- [PATCH v2 14/52] tcg: Split out tcg/oversized-guest.h, Richard Henderson, 2023/05/23
- [PATCH v2 10/52] *: Add missing includes of tcg/debug-assert.h, Richard Henderson, 2023/05/23
- [PATCH v2 13/52] target/arm: Fix test of TCG_OVERSIZED_GUEST, Richard Henderson, 2023/05/23
- [PATCH v2 20/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h, Richard Henderson, 2023/05/23
- [PATCH v2 35/52] tcg: Spit out exec/translation-block.h, Richard Henderson, 2023/05/23