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[PULL 06/23] tcg/mips: Split out tcg_out_movi_two
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From: |
Richard Henderson |
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Subject: |
[PULL 06/23] tcg/mips: Split out tcg_out_movi_two |
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Date: |
Thu, 25 May 2023 11:10:19 -0700 |
Emit all 32-bit signed constants, which can be loaded in two insns.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 35 ++++++++++++++++++++++++-----------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index bbff510c46..7a19f8db1d 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -527,6 +527,22 @@ static bool tcg_out_movi_one(TCGContext *s, TCGReg ret,
tcg_target_long arg)
return false;
}
+static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg)
+{
+ /*
+ * All signed 32-bit constants are loadable with two immediates,
+ * and everything else requires more work.
+ */
+ if (arg == (int32_t)arg) {
+ if (!tcg_out_movi_one(s, ret, arg)) {
+ tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
+ }
+ return true;
+ }
+ return false;
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
@@ -534,21 +550,18 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
arg = (int32_t)arg;
}
- if (tcg_out_movi_one(s, ret, arg)) {
+ /* Load all 32-bit constants. */
+ if (tcg_out_movi_two(s, ret, arg)) {
return;
}
- if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
- tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
+ tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
+ if (arg & 0xffff0000ull) {
+ tcg_out_dsll(s, ret, ret, 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
+ tcg_out_dsll(s, ret, ret, 16);
} else {
- tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
- if (arg & 0xffff0000ull) {
- tcg_out_dsll(s, ret, ret, 16);
- tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
- tcg_out_dsll(s, ret, ret, 16);
- } else {
- tcg_out_dsll(s, ret, ret, 32);
- }
+ tcg_out_dsll(s, ret, ret, 32);
}
if (arg & 0xffff) {
tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
--
2.34.1
- [PULL 00/23] tcg patch queue, Richard Henderson, 2023/05/25
- [PULL 01/23] tcg/mips: Move TCG_AREG0 to S8, Richard Henderson, 2023/05/25
- [PULL 03/23] tcg/mips: Unify TCG_GUEST_BASE_REG tests, Richard Henderson, 2023/05/25
- [PULL 02/23] tcg/mips: Move TCG_GUEST_BASE_REG to S7, Richard Henderson, 2023/05/25
- [PULL 04/23] tcg/mips: Create and use TCG_REG_TB, Richard Henderson, 2023/05/25
- [PULL 06/23] tcg/mips: Split out tcg_out_movi_two,
Richard Henderson <=
- [PULL 05/23] tcg/mips: Split out tcg_out_movi_one, Richard Henderson, 2023/05/25
- [PULL 07/23] tcg/mips: Use the constant pool for 64-bit constants, Richard Henderson, 2023/05/25
- [PULL 08/23] tcg/mips: Aggressively use the constant pool for n64 calls, Richard Henderson, 2023/05/25
- [PULL 09/23] tcg/mips: Try tb-relative addresses in tcg_out_movi, Richard Henderson, 2023/05/25
- [PULL 10/23] tcg/mips: Try three insns with shift and add in tcg_out_movi, Richard Henderson, 2023/05/25
- [PULL 11/23] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF, Richard Henderson, 2023/05/25
- [PULL 12/23] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN, Richard Henderson, 2023/05/25
- [PULL 13/23] disas/riscv: Decode czero.{eqz,nez}, Richard Henderson, 2023/05/25
- [PULL 15/23] tcg/riscv: Support ANDN, ORN, XNOR from Zbb, Richard Henderson, 2023/05/25
- [PULL 14/23] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/25