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[PULL 05/23] tcg/mips: Split out tcg_out_movi_one
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From: |
Richard Henderson |
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Subject: |
[PULL 05/23] tcg/mips: Split out tcg_out_movi_one |
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Date: |
Thu, 25 May 2023 11:10:18 -0700 |
Emit all constants that can be loaded in exactly one insn.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 26 ++++++++++++++++++++------
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 6f03b44ac0..bbff510c46 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -510,20 +510,34 @@ static bool tcg_out_mov(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg)
return true;
}
+static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
+{
+ if (arg == (int16_t)arg) {
+ tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
+ return true;
+ }
+ if (arg == (uint16_t)arg) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
+ return true;
+ }
+ if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
+ tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
+ return true;
+ }
+ return false;
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
}
- if (arg == (int16_t)arg) {
- tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
- return;
- }
- if (arg == (uint16_t)arg) {
- tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
+
+ if (tcg_out_movi_one(s, ret, arg)) {
return;
}
+
if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
} else {
--
2.34.1
- [PULL 00/23] tcg patch queue, Richard Henderson, 2023/05/25
- [PULL 01/23] tcg/mips: Move TCG_AREG0 to S8, Richard Henderson, 2023/05/25
- [PULL 03/23] tcg/mips: Unify TCG_GUEST_BASE_REG tests, Richard Henderson, 2023/05/25
- [PULL 02/23] tcg/mips: Move TCG_GUEST_BASE_REG to S7, Richard Henderson, 2023/05/25
- [PULL 04/23] tcg/mips: Create and use TCG_REG_TB, Richard Henderson, 2023/05/25
- [PULL 06/23] tcg/mips: Split out tcg_out_movi_two, Richard Henderson, 2023/05/25
- [PULL 05/23] tcg/mips: Split out tcg_out_movi_one,
Richard Henderson <=
- [PULL 07/23] tcg/mips: Use the constant pool for 64-bit constants, Richard Henderson, 2023/05/25
- [PULL 08/23] tcg/mips: Aggressively use the constant pool for n64 calls, Richard Henderson, 2023/05/25
- [PULL 09/23] tcg/mips: Try tb-relative addresses in tcg_out_movi, Richard Henderson, 2023/05/25
- [PULL 10/23] tcg/mips: Try three insns with shift and add in tcg_out_movi, Richard Henderson, 2023/05/25
- [PULL 11/23] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF, Richard Henderson, 2023/05/25
- [PULL 12/23] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN, Richard Henderson, 2023/05/25
- [PULL 13/23] disas/riscv: Decode czero.{eqz,nez}, Richard Henderson, 2023/05/25
- [PULL 15/23] tcg/riscv: Support ANDN, ORN, XNOR from Zbb, Richard Henderson, 2023/05/25
- [PULL 14/23] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/25
- [PULL 16/23] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Richard Henderson, 2023/05/25