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[PULL 20/23] tcg/riscv: Support CPOP from Zbb
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From: |
Richard Henderson |
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Subject: |
[PULL 20/23] tcg/riscv: Support CPOP from Zbb |
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Date: |
Thu, 25 May 2023 11:10:33 -0700 |
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.h | 4 ++--
tcg/riscv/tcg-target.c.inc | 9 +++++++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 8e327afc3a..e0b23006c4 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -127,7 +127,7 @@ extern bool have_zbb;
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0
-#define TCG_TARGET_HAS_ctpop_i32 0
+#define TCG_TARGET_HAS_ctpop_i32 have_zbb
#define TCG_TARGET_HAS_brcond2 1
#define TCG_TARGET_HAS_setcond2 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
@@ -161,7 +161,7 @@ extern bool have_zbb;
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0
-#define TCG_TARGET_HAS_ctpop_i64 0
+#define TCG_TARGET_HAS_ctpop_i64 have_zbb
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index cb4afb4733..05ea9fead8 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1511,6 +1511,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_ctpop_i32:
+ tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0);
+ break;
+ case INDEX_op_ctpop_i64:
+ tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0);
+ break;
+
case INDEX_op_add2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], false, true);
@@ -1637,6 +1644,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_bswap16_i64:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
--
2.34.1
- [PULL 09/23] tcg/mips: Try tb-relative addresses in tcg_out_movi, (continued)
- [PULL 09/23] tcg/mips: Try tb-relative addresses in tcg_out_movi, Richard Henderson, 2023/05/25
- [PULL 10/23] tcg/mips: Try three insns with shift and add in tcg_out_movi, Richard Henderson, 2023/05/25
- [PULL 11/23] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF, Richard Henderson, 2023/05/25
- [PULL 12/23] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN, Richard Henderson, 2023/05/25
- [PULL 13/23] disas/riscv: Decode czero.{eqz,nez}, Richard Henderson, 2023/05/25
- [PULL 15/23] tcg/riscv: Support ANDN, ORN, XNOR from Zbb, Richard Henderson, 2023/05/25
- [PULL 14/23] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/25
- [PULL 16/23] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Richard Henderson, 2023/05/25
- [PULL 17/23] tcg/riscv: Use ADD.UW for guest address generation, Richard Henderson, 2023/05/25
- [PULL 18/23] tcg/riscv: Support rotates from Zbb, Richard Henderson, 2023/05/25
- [PULL 20/23] tcg/riscv: Support CPOP from Zbb,
Richard Henderson <=
- [PULL 21/23] tcg/riscv: Improve setcond expansion, Richard Henderson, 2023/05/25
- [PULL 22/23] tcg/riscv: Implement movcond, Richard Henderson, 2023/05/25
- [PULL 23/23] tcg/riscv: Support CTZ, CLZ from Zbb, Richard Henderson, 2023/05/25
- [PULL 19/23] tcg/riscv: Support REV8 from Zbb, Richard Henderson, 2023/05/25
- Re: [PULL 00/23] tcg patch queue, Richard Henderson, 2023/05/25