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[PATCH 06/10] target/tricore: Implement hptof insn
From: |
Bastian Koppelmann |
Subject: |
[PATCH 06/10] target/tricore: Implement hptof insn |
Date: |
Sat, 26 Aug 2023 18:02:38 +0200 |
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 39 +++++++++++++++++++++++
target/tricore/helper.h | 1 +
target/tricore/translate.c | 7 ++++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_hptof.S | 12 +++++++
6 files changed, 61 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_hptof.S
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 3db2341ac0..b91f872396 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -29,6 +29,8 @@
#define MUL_NAN 0x7fc00002
#define HP_NEG_INFINITY 0xfc00
#define HP_POS_INFINITY 0x7c00
+#define NEG_INFINITY 0xff800000
+#define POS_INFINITY 0x7f800000
#define FPU_FS PSW_USB_C
#define FPU_FI PSW_USB_V
#define FPU_FV PSW_USB_SV
@@ -375,6 +377,43 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)result;
}
+uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
+{
+ float16 f_arg = make_float16(arg);
+ uint32_t result = 0;
+ int32_t flags = 0;
+
+ if (float16_is_any_nan(f_arg)) {
+ if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
+ flags |= float_flag_invalid;
+ }
+ result = 0;
+ result = float32_set_sign(result, f_arg >> 15);
+ result = deposit32(result, 23, 8, 0xff);
+ result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
+ result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
+ } else if (float16_is_infinity(f_arg)) {
+ if (float16_is_neg(f_arg)) {
+ result = NEG_INFINITY;
+ } else {
+ result = POS_INFINITY;
+ }
+ } else {
+ set_flush_inputs_to_zero(0, &env->fp_status);
+ result = float16_to_float32(f_arg, true, &env->fp_status);
+ set_flush_inputs_to_zero(1, &env->fp_status);
+ flags = f_get_excp_flags(env);
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+
+ return result;
+}
+
uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index dcc5a492b3..1d97d078b0 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -112,6 +112,7 @@ DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(ftohp, i32, env, i32)
+DEF_HELPER_2(hptof, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d94c273f89..4400d2c3cb 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6271,6 +6271,13 @@ static void decode_rr_divide(DisasContext *ctx)
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_HPTOF:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 29e655a667..60d2402b6e 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1153,6 +1153,7 @@ enum {
OPC2_32_RR_CMP_F = 0x00,
OPC2_32_RR_FTOIZ = 0x13,
OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
+ OPC2_32_RR_HPTOF = 0x24, /* 1.6.2 only */
OPC2_32_RR_FTOQ31 = 0x11,
OPC2_32_RR_FTOQ31Z = 0x18,
OPC2_32_RR_FTOU = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target
b/tests/tcg/tricore/Makefile.softmmu-target
index f4a27a83e4..afcf41a977 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -17,6 +17,7 @@ TESTS += test_fmul.asm.tst
TESTS += test_ftohp.asm.tst
TESTS += test_ftoi.asm.tst
TESTS += test_ftou.asm.tst
+TESTS += test_hptof.asm.tst
TESTS += test_imask.asm.tst
TESTS += test_insert.asm.tst
TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_hptof.S
b/tests/tcg/tricore/asm/test_hptof.S
new file mode 100644
index 0000000000..8adc5e5273
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_hptof.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(hptof, 1, 0xba190000, 0xcc0e90c8)
+ TEST_D_D(hptof, 2, 0x3eaea000, 0x8be23575)
+ TEST_D_D(hptof, 3, 0xc33b8000, 0xcc48d9dc)
+ TEST_D_D(hptof, 4, 0x43e2a000, 0xaef95f15)
+ TEST_D_D(hptof, 5, 0x3d55e000, 0x04932aaf)
+
+ TEST_PASSFAIL
+
--
2.41.0
[PATCH 06/10] target/tricore: Implement hptof insn,
Bastian Koppelmann <=
[PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0, Bastian Koppelmann, 2023/08/26
[PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT, Bastian Koppelmann, 2023/08/26
[PATCH 09/10] target/tricore: Replace cpu_*_code with translator_*, Bastian Koppelmann, 2023/08/26
[PATCH 10/10] target/tricore: Fix FTOUZ being ISA v1.3.1 up, Bastian Koppelmann, 2023/08/26