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Re: [PATCH RESEND v8 10/20] target/riscv: add 'max' CPU type
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From: |
Andrew Jones |
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Subject: |
Re: [PATCH RESEND v8 10/20] target/riscv: add 'max' CPU type |
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Date: |
Thu, 31 Aug 2023 15:11:03 +0200 |
On Thu, Aug 24, 2023 at 07:14:30PM -0300, Daniel Henrique Barboza wrote:
> The 'max' CPU type is used by tooling to determine what's the most
> capable CPU a current QEMU version implements. Other archs such as ARM
> implements this type. Let's add it to RISC-V.
>
> What we consider "most capable CPU" in this context are related to
> ratified, non-vendor extensions. This means that we want the 'max' CPU
> to enable all (possible) ratified extensions by default. The reasoning
> behind this design is (1) vendor extensions can conflict with each other
> and we won't play favorities deciding which one is default or not and
> (2) non-ratified extensions are always prone to changes, not being
> stable enough to be enabled by default.
>
> All this said, we're still not able to enable all ratified extensions
> due to conflicts between them. Zfinx and all its dependencies aren't
> enabled because of a conflict with RVF. zce, zcmp and zcmt are also
> disabled due to RVD conflicts. When running with 64 bits we're also
> disabling zcf.
>
> MISA bits RVG, RVJ and RVV are also being set manually since they're
> default disabled.
>
> This is the resulting 'riscv,isa' DT for this new CPU:
>
> rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
> zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
> zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
> smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 56 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 57 insertions(+)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
- [PATCH RESEND v8 06/20] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], (continued)
- [PATCH RESEND v8 06/20] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 07/20] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array(), Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 08/20] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array(), Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 09/20] target/riscv/cpu.c: limit cfg->vext_spec log message, Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 14/20] target/riscv: make CPUCFG() macro public, Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 10/20] target/riscv: add 'max' CPU type, Daniel Henrique Barboza, 2023/08/24
- Re: [PATCH RESEND v8 10/20] target/riscv: add 'max' CPU type,
Andrew Jones <=
- [PATCH RESEND v8 16/20] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize(), Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 12/20] target/riscv: deprecate the 'any' CPU type, Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 11/20] avocado, risc-v: add opensbi tests for 'max' CPU, Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 13/20] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled, Daniel Henrique Barboza, 2023/08/24
- [PATCH RESEND v8 15/20] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update(), Daniel Henrique Barboza, 2023/08/24