Re: [PULL 00/65] riscv-to-apply queue

[Michael Tokarev]

08.09.2023 09:03, Alistair Francis wrote:

> Akihiko Odaki (1):
>        target/riscv: Allocate itrigger timers only once
>
> Ard Biesheuvel (2):
>        target/riscv: Use existing lookup tables for MixColumns
>        target/riscv: Use accelerated helper for AES64KS1I
>
> Conor Dooley (1):
>        hw/riscv: virt: Fix riscv,pmu DT node path
>
> Daniel Henrique Barboza (26):
>        target/riscv/cpu.c: do not run 'host' CPU with TCG
>        target/riscv/cpu.c: add zmmul isa string
>        target/riscv/cpu.c: add smepmp isa string
>        target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
>        hw/riscv/virt.c: fix non-KVM --enable-debug build
>        hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
>        target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
>        target/riscv/cpu.c: skip 'bool' check when filtering KVM props
>        target/riscv/cpu.c: split kvm prop handling to its own helper
>        target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
>        target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
>        target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
>        target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
>        target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
>        target/riscv/cpu.c: limit cfg->vext_spec log message
>        target/riscv: add 'max' CPU type
>        avocado, risc-v: add tuxboot tests for 'max' CPU
>        target/riscv: deprecate the 'any' CPU type
>        target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
>        target/riscv: make CPUCFG() macro public
>        target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
>        target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
>        target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
>        target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
>        target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
>        target/riscv/cpu.c: consider user option with RVG
>
> Dickon Hood (2):
>        target/riscv: Refactor translation of vector-widening instruction
>        target/riscv: Add Zvbb ISA extension support
>
> Jason Chien (3):
>        target/riscv: Add Zihintntl extension ISA string to DTS
>        hw/intc: Fix upper/lower mtime write calculation
>        hw/intc: Make rtc variable names consistent
>
> Kiran Ostrolenk (4):
>        target/riscv: Refactor some of the generic vector functionality
>        target/riscv: Refactor vector-vector translation macro
>        target/riscv: Refactor some of the generic vector functionality
>        target/riscv: Add Zvknh ISA extension support
>
> LIU Zhiwei (3):
>        target/riscv: Fix page_check_range use in fault-only-first
>        target/riscv: Fix zfa fleq.d and fltq.d
>        linux-user/riscv: Use abi type for target_ucontext
>
> Lawrence Hunter (2):
>        target/riscv: Add Zvbc ISA extension support
>        target/riscv: Add Zvksh ISA extension support
>
> Leon Schuermann (1):
>        target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
>
> Max Chou (3):
>        crypto: Create sm4_subword
>        crypto: Add SM4 constant parameter CK
>        target/riscv: Add Zvksed ISA extension support
>
> Nazar Kazakov (4):
>        target/riscv: Remove redundant "cpu_vl == 0" checks
>        target/riscv: Move vector translation checks
>        target/riscv: Add Zvkned ISA extension support
>        target/riscv: Add Zvkg ISA extension support
>
> Nikita Shubin (1):
>        target/riscv: don't read CSR in riscv_csrrw_do64
>
> Rob Bradford (1):
>        target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
>
> Robbin Ehn (1):
>        linux-user/riscv: Add new extensions to hwprobe
>
> Thomas Huth (2):
>        hw/char/riscv_htif: Fix printing of console characters on big endian 
> hosts
>        hw/char/riscv_htif: Fix the console syscall on big endian hosts
>
> Tommy Wu (1):
>        target/riscv: Align the AIA model to v1.0 ratified spec
>
> Vineet Gupta (1):
>        riscv: zicond: make non-experimental
>
> Weiwei Li (1):
>        target/riscv: Update CSR bits name for svadu extension
>
> Yong-Xuan Wang (5):
>        target/riscv: support the AIA device emulation with KVM enabled
>        target/riscv: check the in-kernel irqchip support
>        target/riscv: Create an KVM AIA irqchip
>        target/riscv: update APLIC and IMSIC to support KVM AIA
>        target/riscv: select KVM AIA in riscv virt machine

From the above, it looks like the following are candidates for -stable:

 02/65 hw/char/riscv_htif: Fix printing of console characters on big endian 
hosts
 06/65 target/riscv: Fix page_check_range use in fault-only-first
 25/65 target/riscv: Fix zfa fleq.d and fltq.d
 26/65 hw/intc: Fix upper/lower mtime write calculation
 27/65 hw/intc: Make rtc variable names consistent
   (not really necessary but completes the previous change)
 28/65 linux-user/riscv: Use abi type for target_ucontext
 34/65 hw/riscv: virt: Fix riscv,pmu DT node path
 36/65 target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0

Also maybe:

 38/65 hw/riscv/virt.c: fix non-KVM --enable-debug build
 39/65 hw/intc/riscv_aplic.c fix non-KVM --enable-debug build

Please let me know if either something from the above list should not
be pickled up for stable, or something else should be added there.

Thank you!

/mjt