[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 05/45] target/riscv/cpu.c: add smepmp isa string
|
From: |
Alistair Francis |
|
Subject: |
[PULL v2 05/45] target/riscv/cpu.c: add smepmp isa string |
|
Date: |
Mon, 11 Sep 2023 16:42:40 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6d02e85102..921c19e6cd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -130,6 +130,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
+ ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
--
2.41.0
- [PULL v2 00/45] riscv-to-apply queue, Alistair Francis, 2023/09/11
- [PULL v2 01/45] target/riscv/cpu.c: do not run 'host' CPU with TCG, Alistair Francis, 2023/09/11
- [PULL v2 02/45] hw/char/riscv_htif: Fix printing of console characters on big endian hosts, Alistair Francis, 2023/09/11
- [PULL v2 03/45] hw/char/riscv_htif: Fix the console syscall on big endian hosts, Alistair Francis, 2023/09/11
- [PULL v2 04/45] target/riscv/cpu.c: add zmmul isa string, Alistair Francis, 2023/09/11
- [PULL v2 05/45] target/riscv/cpu.c: add smepmp isa string,
Alistair Francis <=
- [PULL v2 06/45] target/riscv: Fix page_check_range use in fault-only-first, Alistair Francis, 2023/09/11
- [PULL v2 07/45] target/riscv: Use existing lookup tables for MixColumns, Alistair Francis, 2023/09/11
- [PULL v2 08/45] target/riscv: Refactor some of the generic vector functionality, Alistair Francis, 2023/09/11
- [PULL v2 09/45] target/riscv: Refactor vector-vector translation macro, Alistair Francis, 2023/09/11
- [PULL v2 10/45] target/riscv: Remove redundant "cpu_vl == 0" checks, Alistair Francis, 2023/09/11
- [PULL v2 11/45] target/riscv: Add Zvbc ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 12/45] target/riscv: Move vector translation checks, Alistair Francis, 2023/09/11
- [PULL v2 13/45] target/riscv: Refactor translation of vector-widening instruction, Alistair Francis, 2023/09/11
- [PULL v2 14/45] target/riscv: Refactor some of the generic vector functionality, Alistair Francis, 2023/09/11
- [PULL v2 15/45] target/riscv: Add Zvbb ISA extension support, Alistair Francis, 2023/09/11