[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v6 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr
From: |
Song Gao |
Subject: |
[PATCH v6 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr |
Date: |
Thu, 14 Sep 2023 10:26:39 +0800 |
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/insns.decode | 7 +
target/loongarch/disas.c | 17 ++
target/loongarch/translate.c | 13 ++
target/loongarch/insn_trans/trans_vec.c.inc | 208 ++++----------------
4 files changed, 75 insertions(+), 170 deletions(-)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index ad6751fdfb..bb3bb447ae 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1976,6 +1976,13 @@ xvsetallnez_h 0111 01101001 11001 01101 ..... 00 ...
@cv
xvsetallnez_w 0111 01101001 11001 01110 ..... 00 ... @cv
xvsetallnez_d 0111 01101001 11001 01111 ..... 00 ... @cv
+xvinsgr2vr_w 0111 01101110 10111 10 ... ..... ..... @vr_ui3
+xvinsgr2vr_d 0111 01101110 10111 110 .. ..... ..... @vr_ui2
+xvpickve2gr_w 0111 01101110 11111 10 ... ..... ..... @rv_ui3
+xvpickve2gr_d 0111 01101110 11111 110 .. ..... ..... @rv_ui2
+xvpickve2gr_wu 0111 01101111 00111 10 ... ..... ..... @rv_ui3
+xvpickve2gr_du 0111 01101111 00111 110 .. ..... ..... @rv_ui2
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index abe113b150..04f9f9fa4b 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1738,6 +1738,16 @@ static void output_vv_x(DisasContext *ctx, arg_vv *a,
const char *mnemonic)
output(ctx, mnemonic, "x%d, x%d", a->vd, a->vj);
}
+static void output_vr_i_x(DisasContext *ctx, arg_vr_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "x%d, r%d, 0x%x", a->vd, a->rj, a->imm);
+}
+
+static void output_rv_i_x(DisasContext *ctx, arg_rv_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, x%d, 0x%x", a->rd, a->vj, a->imm);
+}
+
INSN_LASX(xvadd_b, vvv)
INSN_LASX(xvadd_h, vvv)
INSN_LASX(xvadd_w, vvv)
@@ -2497,6 +2507,13 @@ INSN_LASX(xvsetallnez_h, cv)
INSN_LASX(xvsetallnez_w, cv)
INSN_LASX(xvsetallnez_d, cv)
+INSN_LASX(xvinsgr2vr_w, vr_i)
+INSN_LASX(xvinsgr2vr_d, vr_i)
+INSN_LASX(xvpickve2gr_w, rv_i)
+INSN_LASX(xvpickve2gr_d, rv_i)
+INSN_LASX(xvpickve2gr_wu, rv_i)
+INSN_LASX(xvpickve2gr_du, rv_i)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 10e2fe8ff6..4892834d0c 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -37,6 +37,19 @@ static inline int vec_full_offset(int regno)
return offsetof(CPULoongArchState, fpr[regno]);
}
+static inline int vec_reg_offset(int regno, int index, MemOp mop)
+{
+ const uint8_t size = 1 << mop;
+ int offs = index * size;
+
+#if HOST_BIG_ENDIAN
+ if (size < 8 ) {
+ offs ^ = (8 - size);
+ }
+#endif
+ return offs + vec_full_offset(regno);
+}
+
static inline void get_vreg64(TCGv_i64 dest, int regno, int index)
{
tcg_gen_ld_i64(dest, cpu_env,
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc
b/target/loongarch/insn_trans/trans_vec.c.inc
index 0dec3dfffe..e1ba54075e 100644
--- a/target/loongarch/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
@@ -4829,209 +4829,77 @@ TRANS(xvsetallnez_h, LASX, gen_cx,
gen_helper_vsetallnez_h)
TRANS(xvsetallnez_w, LASX, gen_cx, gen_helper_vsetallnez_w)
TRANS(xvsetallnez_d, LASX, gen_cx, gen_helper_vsetallnez_d)
-static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
+static bool gen_g2v_vl(DisasContext *ctx, arg_vr_i *a, uint32_t oprsz, MemOp
mop,
+ void (*func)(TCGv, TCGv_ptr, tcg_target_long))
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_st8_i64(src, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm)));
- return true;
-}
-
-static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)
-{
- TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_st16_i64(src, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm)));
- return true;
-}
-
-static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
-{
- TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
+ if (!check_vec(ctx, oprsz)) {
return true;
}
- tcg_gen_st32_i64(src, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)));
- return true;
-}
-
-static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
-{
- TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
+ func(src, cpu_env, vec_reg_offset(a->vd, a->imm, mop));
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_st_i64(src, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm)));
return true;
}
-static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)
+static bool gen_g2v(DisasContext *ctx, arg_vr_i *a, MemOp mop,
+ void (*func)(TCGv, TCGv_ptr, tcg_target_long))
{
- TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_ld8s_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
- return true;
+ return gen_g2v_vl(ctx, a, 16, mop, func);
}
-static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)
+static bool gen_g2x(DisasContext *ctx, arg_vr_i *a, MemOp mop,
+ void (*func)(TCGv, TCGv_ptr, tcg_target_long))
{
- TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_ld16s_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
- return true;
+ return gen_g2v_vl(ctx, a, 32, mop, func);
}
-static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
-{
- TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
+TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64)
+TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64)
+TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_i64)
+TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64)
+TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_i64)
+TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64)
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_ld32s_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
- return true;
-}
-
-static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
+static bool gen_v2g_vl(DisasContext *ctx, arg_rv_i *a, uint32_t oprsz, MemOp
mop,
+ void (*func)(TCGv, TCGv_ptr, tcg_target_long))
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
+ if (!check_vec(ctx, oprsz)) {
return true;
}
- tcg_gen_ld_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
- return true;
-}
+ func(dst, cpu_env, vec_reg_offset(a->vj, a->imm, mop));
-static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)
-{
- TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_ld8u_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}
-static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)
+static bool gen_v2g(DisasContext *ctx, arg_rv_i *a, MemOp mop,
+ void (*func)(TCGv, TCGv_ptr, tcg_target_long))
{
- TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_ld16u_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
- return true;
+ return gen_v2g_vl(ctx, a, 16, mop, func);
}
-static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
+static bool gen_x2g(DisasContext *ctx, arg_rv_i *a, MemOp mop,
+ void (*func)(TCGv, TCGv_ptr, tcg_target_long))
{
- TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_ld32u_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
- return true;
+ return gen_v2g_vl(ctx, a, 32, mop, func);
}
-static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
-{
- TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
-
- if (!avail_LSX(ctx)) {
- return false;
- }
-
- if (!check_vec(ctx, 16)) {
- return true;
- }
-
- tcg_gen_ld_i64(dst, cpu_env,
- offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
- return true;
-}
+TRANS(vpickve2gr_b, LSX, gen_v2g, MO_8, tcg_gen_ld8s_i64)
+TRANS(vpickve2gr_h, LSX, gen_v2g, MO_16, tcg_gen_ld16s_i64)
+TRANS(vpickve2gr_w, LSX, gen_v2g, MO_32, tcg_gen_ld32s_i64)
+TRANS(vpickve2gr_d, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
+TRANS(vpickve2gr_bu, LSX, gen_v2g, MO_8, tcg_gen_ld8u_i64)
+TRANS(vpickve2gr_hu, LSX, gen_v2g, MO_16, tcg_gen_ld16u_i64)
+TRANS(vpickve2gr_wu, LSX, gen_v2g, MO_32, tcg_gen_ld32u_i64)
+TRANS(vpickve2gr_du, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
+TRANS(xvpickve2gr_w, LASX, gen_x2g, MO_32, tcg_gen_ld32s_i64)
+TRANS(xvpickve2gr_d, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
+TRANS(xvpickve2gr_wu, LASX, gen_x2g, MO_32, tcg_gen_ld32u_i64)
+TRANS(xvpickve2gr_du, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
uint32_t oprsz, MemOp mop)
--
2.39.1
- [PATCH v6 36/57] target/loongarch: Implement xvsllwil xvextl, (continued)
- [PATCH v6 36/57] target/loongarch: Implement xvsllwil xvextl, Song Gao, 2023/09/13
- [PATCH v6 38/57] target/loongarch: Implement xvsrln xvsran, Song Gao, 2023/09/13
- [PATCH v6 33/57] target/loognarch: Implement xvldi, Song Gao, 2023/09/13
- [PATCH v6 42/57] target/loongarch: Implement xvclo xvclz, Song Gao, 2023/09/13
- [PATCH v6 43/57] target/loongarch: Implement xvpcnt, Song Gao, 2023/09/13
- [PATCH v6 57/57] target/loongarch: CPUCFG support LASX, Song Gao, 2023/09/13
- [PATCH v6 50/57] target/loongarch: Implement xvbitsel xvset, Song Gao, 2023/09/13
- [PATCH v6 56/57] target/loongarch: Move simply DO_XX marcos togther, Song Gao, 2023/09/13
- [PATCH v6 32/57] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz, Song Gao, 2023/09/13
- [PATCH v6 44/57] target/loongarch: Implement xvbitclr xvbitset xvbitrev, Song Gao, 2023/09/13
- [PATCH v6 51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr,
Song Gao <=
- [PATCH v6 54/57] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i, Song Gao, 2023/09/13
- [PATCH v6 35/57] target/loongarch: Implement xvsll xvsrl xvsra xvrotr, Song Gao, 2023/09/13
- [PATCH v6 41/57] target/loongarch: Implement xvssrlrn xvssrarn, Song Gao, 2023/09/13
- [PATCH v6 48/57] target/loongarch: Implement xvseq xvsle xvslt, Song Gao, 2023/09/13
- [PATCH v6 52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve, Song Gao, 2023/09/13