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[PATCH 05/19] hw/pci-bridge/cxl_upstream: Move defintion of device to he
From: |
Jonathan Cameron |
Subject: |
[PATCH 05/19] hw/pci-bridge/cxl_upstream: Move defintion of device to header. |
Date: |
Mon, 25 Sep 2023 17:11:10 +0100 |
To avoid repetition of switch upstream port specific data in the
CXLDeviceState structure it will be necessary to access the switch USP
specific data from mailbox callbacks. Hence move it to cxl_device.h so it
is no longer an opaque structure.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
include/hw/pci-bridge/cxl_upstream_port.h | 18 ++++++++++++++++++
hw/pci-bridge/cxl_upstream.c | 11 +----------
2 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/include/hw/pci-bridge/cxl_upstream_port.h
b/include/hw/pci-bridge/cxl_upstream_port.h
new file mode 100644
index 0000000000..b02aa8f659
--- /dev/null
+++ b/include/hw/pci-bridge/cxl_upstream_port.h
@@ -0,0 +1,18 @@
+
+#ifndef CXL_USP_H
+#define CXL_USP_H
+#include "hw/pci/pcie.h"
+#include "hw/pci/pcie_port.h"
+#include "hw/cxl/cxl.h"
+
+typedef struct CXLUpstreamPort {
+ /*< private >*/
+ PCIEPort parent_obj;
+
+ /*< public >*/
+ CXLComponentState cxl_cstate;
+ DOECap doe_cdat;
+ uint64_t sn;
+} CXLUpstreamPort;
+
+#endif /* CXL_SUP_H */
diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c
index b81bb5fec9..36737189c6 100644
--- a/hw/pci-bridge/cxl_upstream.c
+++ b/hw/pci-bridge/cxl_upstream.c
@@ -14,6 +14,7 @@
#include "hw/pci/msi.h"
#include "hw/pci/pcie.h"
#include "hw/pci/pcie_port.h"
+#include "hw/pci-bridge/cxl_upstream_port.h"
/*
* Null value of all Fs suggested by IEEE RA guidelines for use of
* EU, OUI and CID
@@ -30,16 +31,6 @@
#define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
(CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF)
-typedef struct CXLUpstreamPort {
- /*< private >*/
- PCIEPort parent_obj;
-
- /*< public >*/
- CXLComponentState cxl_cstate;
- DOECap doe_cdat;
- uint64_t sn;
-} CXLUpstreamPort;
-
CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp)
{
return &usp->cxl_cstate;
--
2.39.2
- [PATCH 00/19] QEMU: CXL mailbox rework and features, Jonathan Cameron, 2023/09/25
- [PATCH 01/19] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant, Jonathan Cameron, 2023/09/25
- [PATCH 02/19] hw/cxl/mbox: Split mailbox command payload into separate input and output, Jonathan Cameron, 2023/09/25
- [PATCH 03/19] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState, Jonathan Cameron, 2023/09/25
- [PATCH 04/19] hw/cxl/mbox: Generalize the CCI command processing, Jonathan Cameron, 2023/09/25
- [PATCH 05/19] hw/pci-bridge/cxl_upstream: Move defintion of device to header.,
Jonathan Cameron <=
- [PATCH 06/19] hw/cxl/i2c_mctp_cxl: Initial device emulation, Jonathan Cameron, 2023/09/25
- [PATCH 07/19] hw/cxl/mbox: Add Information and Status / Identify command, Jonathan Cameron, 2023/09/25
- [PATCH 08/19] docs: cxl: Add example commandline for MCTP CXL CCIs, Jonathan Cameron, 2023/09/25
- [PATCH 09/19] hw/cxl/mbox: Add Physical Switch Identify command., Jonathan Cameron, 2023/09/25
- [PATCH 10/19] hw/cxl: Add a switch mailbox CCI function, Jonathan Cameron, 2023/09/25
- [PATCH 11/19] hw/pci-bridge/cxl_downstream: Set default link width and link speed, Jonathan Cameron, 2023/09/25
- [PATCH 12/19] hw/cxl: Implement Physical Ports status retrieval, Jonathan Cameron, 2023/09/25
- [PATCH 13/19] hw/cxl/mbox: Add Get Background Operation Status Command, Jonathan Cameron, 2023/09/25