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[PULL v2 39/53] hw/pci-bridge/cxl-upstream: Add serial number extended c
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From: |
Michael S. Tsirkin |
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Subject: |
[PULL v2 39/53] hw/pci-bridge/cxl-upstream: Add serial number extended capability support |
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Date: |
Wed, 4 Oct 2023 23:45:05 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Will be needed so there is a defined serial number for
information queries via the Switch CCI.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230913133615.29876-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/pci-bridge/cxl_upstream.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c
index 2b9cf0cc97..a57806fb31 100644
--- a/hw/pci-bridge/cxl_upstream.c
+++ b/hw/pci-bridge/cxl_upstream.c
@@ -14,14 +14,21 @@
#include "hw/pci/msi.h"
#include "hw/pci/pcie.h"
#include "hw/pci/pcie_port.h"
+/*
+ * Null value of all Fs suggested by IEEE RA guidelines for use of
+ * EU, OUI and CID
+ */
+#define UI64_NULL (~0ULL)
#define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 2
#define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70
#define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90
#define CXL_UPSTREAM_PORT_AER_OFFSET 0x100
-#define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
+#define CXL_UPSTREAM_PORT_SN_OFFSET \
(CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
+#define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
+ (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF)
typedef struct CXLUpstreamPort {
/*< private >*/
@@ -30,6 +37,7 @@ typedef struct CXLUpstreamPort {
/*< public >*/
CXLComponentState cxl_cstate;
DOECap doe_cdat;
+ uint64_t sn;
} CXLUpstreamPort;
CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp)
@@ -326,7 +334,9 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp)
if (rc) {
goto err_cap;
}
-
+ if (usp->sn != UI64_NULL) {
+ pcie_dev_ser_num_init(d, CXL_UPSTREAM_PORT_SN_OFFSET, usp->sn);
+ }
cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET;
cxl_cstate->pdev = d;
build_dvsecs(cxl_cstate);
@@ -366,6 +376,7 @@ static void cxl_usp_exitfn(PCIDevice *d)
}
static Property cxl_upstream_props[] = {
+ DEFINE_PROP_UINT64("sn", CXLUpstreamPort, sn, UI64_NULL),
DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename),
DEFINE_PROP_END_OF_LIST()
};
--
MST
- Re: [PULL v2 29/53] hw/i386: Remove now redundant TYPE_ACPI_GED_X86, (continued)
[PULL v2 31/53] hw/acpi: Trace GPE access in all device models, not just PIIX4, Michael S. Tsirkin, 2023/10/04
[PULL v2 30/53] hw/i386/acpi-build: Determine SMI command port just once, Michael S. Tsirkin, 2023/10/04
[PULL v2 32/53] hw/acpi/core: Trace enable and status registers of GPE separately, Michael S. Tsirkin, 2023/10/04
[PULL v2 34/53] vdpa net: zero vhost_vdpa iova_tree pointer at cleanup, Michael S. Tsirkin, 2023/10/04
[PULL v2 33/53] vdpa: fix gcc cvq_isolated uninitialized variable warning, Michael S. Tsirkin, 2023/10/04
[PULL v2 40/53] vdpa net: fix error message setting virtio status, Michael S. Tsirkin, 2023/10/04
[PULL v2 45/53] pcie_sriov: unregister_vfs(): fix error path, Michael S. Tsirkin, 2023/10/04
[PULL v2 39/53] hw/pci-bridge/cxl-upstream: Add serial number extended capability support,
Michael S. Tsirkin <=
[PULL v2 42/53] vdpa net: follow VirtIO initialization properly at cvq isolation probing, Michael S. Tsirkin, 2023/10/04
[PULL v2 36/53] hw/cxl: Add utility functions decoder interleave ways and target count., Michael S. Tsirkin, 2023/10/04
[PULL v2 37/53] hw/cxl: Fix and use same calculation for HDM decoder block size everywhere, Michael S. Tsirkin, 2023/10/04
[PULL v2 35/53] hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c, Michael S. Tsirkin, 2023/10/04
[PULL v2 38/53] hw/cxl: Support 4 HDM decoders at all levels of topology, Michael S. Tsirkin, 2023/10/04
[PULL v2 41/53] vdpa net: stop probing if cannot set features, Michael S. Tsirkin, 2023/10/04
[PULL v2 46/53] libvhost-user.c: add assertion to vu_message_read_default, Michael S. Tsirkin, 2023/10/04
[PULL v2 43/53] amd_iommu: Fix APIC address check, Michael S. Tsirkin, 2023/10/04