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[PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
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From: |
Alistair Francis |
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Subject: |
[PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' |
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Date: |
Thu, 12 Oct 2023 14:10:35 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The array isn't marked as 'const' because we're initializing their
elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
fields.
In a closer look we can see that we're not using these 2 fields after
creating the MISA properties. And we can create the properties by using
riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
directly.
Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
and make misa_ext_cfgs[] a const array.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 40f9ad84f6..1c42e2590e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1208,8 +1208,6 @@ static void riscv_cpu_init(Object *obj)
}
typedef struct RISCVCPUMisaExtConfig {
- const char *name;
- const char *description;
target_ulong misa_bit;
bool enabled;
} RISCVCPUMisaExtConfig;
@@ -1313,7 +1311,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
#define MISA_CFG(_bit, _enabled) \
{.misa_bit = _bit, .enabled = _enabled}
-static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
MISA_CFG(RVA, true),
MISA_CFG(RVC, true),
MISA_CFG(RVD, true),
@@ -1340,25 +1338,22 @@ void riscv_cpu_add_misa_properties(Object *cpu_obj)
int i;
for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
- RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+ const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
int bit = misa_cfg->misa_bit;
-
- misa_cfg->name = riscv_get_misa_ext_name(bit);
- misa_cfg->description = riscv_get_misa_ext_description(bit);
+ const char *name = riscv_get_misa_ext_name(bit);
+ const char *desc = riscv_get_misa_ext_description(bit);
/* Check if KVM already created the property */
- if (object_property_find(cpu_obj, misa_cfg->name)) {
+ if (object_property_find(cpu_obj, name)) {
continue;
}
- object_property_add(cpu_obj, misa_cfg->name, "bool",
+ object_property_add(cpu_obj, name, "bool",
cpu_get_misa_ext_cfg,
cpu_set_misa_ext_cfg,
NULL, (void *)misa_cfg);
- object_property_set_description(cpu_obj, misa_cfg->name,
- misa_cfg->description);
- object_property_set_bool(cpu_obj, misa_cfg->name,
- misa_cfg->enabled, NULL);
+ object_property_set_description(cpu_obj, name, desc);
+ object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
}
}
--
2.41.0
- [PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c, (continued)
- [PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/10/12
- [PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const', Alistair Francis, 2023/10/12
- [PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Alistair Francis, 2023/10/12
- [PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public, Alistair Francis, 2023/10/12
- [PULL 32/54] target/riscv: remove kvm-stub.c, Alistair Francis, 2023/10/12
- [PULL 33/54] target/riscv: introduce KVM AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 34/54] target/riscv: move KVM only files to kvm subdir, Alistair Francis, 2023/10/12
- [PULL 35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties(), Alistair Francis, 2023/10/12
- [PULL 36/54] target/riscv/cpu.c: export set_misa(), Alistair Francis, 2023/10/12
- [PULL 37/54] target/riscv/tcg: introduce tcg_cpu_instance_init(), Alistair Francis, 2023/10/12
- [PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const',
Alistair Francis <=
- [PULL 39/54] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 40/54] target/riscv/cpu.c: export isa_edata_arr[], Alistair Francis, 2023/10/12
- [PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 42/54] target/riscv: add riscv_cpu_get_name(), Alistair Francis, 2023/10/12
- [PULL 43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus, Alistair Francis, 2023/10/12
- [PULL 46/54] hw/misc/sifive_test.c: replace exit calls with proper shutdown, Alistair Francis, 2023/10/12
- [PULL 45/54] softmmu: pass the main loop status to gdb "Wxx" packet, Alistair Francis, 2023/10/12
- [PULL 47/54] hw/char: riscv_htif: replace exit calls with proper shutdown, Alistair Francis, 2023/10/12
- [PULL 44/54] softmmu: add means to pass an exit code when requesting a shutdown, Alistair Francis, 2023/10/12
- [PULL 48/54] gdbstub: replace exit calls with proper shutdown for softmmu, Alistair Francis, 2023/10/12