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[PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond
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From: |
Richard Henderson |
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Subject: |
[PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond |
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Date: |
Fri, 13 Oct 2023 14:27:34 -0700 |
Fold the condition into the branch or movcond when possible.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 32 +++++++++++++-------------------
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index ee8c0450aa..5cea835b28 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2855,14 +2855,15 @@ static bool advance_jump_uncond_always(DisasContext
*dc, bool annul,
return true;
}
-static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest)
+static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp,
+ bool annul, target_ulong dest)
{
target_ulong npc = dc->npc;
if (annul) {
TCGLabel *l1 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
+ tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1);
gen_goto_tb(dc, 0, npc, dest);
gen_set_label(l1);
gen_goto_tb(dc, 1, npc + 4, npc + 8);
@@ -2875,8 +2876,8 @@ static bool advance_jump_cond(DisasContext *dc, bool
annul, target_ulong dest)
case DYNAMIC_PC_LOOKUP:
tcg_gen_mov_tl(cpu_pc, cpu_npc);
tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc,
- cpu_cond, tcg_constant_tl(0),
+ tcg_gen_movcond_tl(cmp->cond, cpu_npc,
+ cmp->c1, cmp->c2,
tcg_constant_tl(dest), cpu_npc);
dc->pc = npc;
break;
@@ -2888,6 +2889,11 @@ static bool advance_jump_cond(DisasContext *dc, bool
annul, target_ulong dest)
dc->jump_pc[0] = dest;
dc->jump_pc[1] = npc + 4;
dc->npc = JUMP_PC;
+ if (cmp->is_bool) {
+ tcg_gen_mov_tl(cpu_cond, cmp->c1);
+ } else {
+ tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
+ }
}
}
return true;
@@ -2910,12 +2916,7 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a)
flush_cond(dc);
gen_compare(&cmp, a->cc, a->cond, dc);
- if (cmp.is_bool) {
- tcg_gen_mov_tl(cpu_cond, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
- }
- return advance_jump_cond(dc, a->a, target);
+ return advance_jump_cond(dc, &cmp, a->a, target);
}
}
@@ -2942,12 +2943,7 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
flush_cond(dc);
gen_fcompare(&cmp, a->cc, a->cond);
- if (cmp.is_bool) {
- tcg_gen_mov_tl(cpu_cond, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
- }
- return advance_jump_cond(dc, a->a, target);
+ return advance_jump_cond(dc, &cmp, a->a, target);
}
}
@@ -2974,9 +2970,7 @@ static bool trans_BPr(DisasContext *dc, arg_BPr *a)
flush_cond(dc);
gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
- tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
-
- return advance_jump_cond(dc, a->a, target);
+ return advance_jump_cond(dc, &cmp, a->a, target);
}
static bool trans_CALL(DisasContext *dc, arg_CALL *a)
--
2.34.1
- [PATCH 03/85] target/sparc: Remove always-set cpu features, (continued)
- [PATCH 03/85] target/sparc: Remove always-set cpu features, Richard Henderson, 2023/10/13
- [PATCH 04/85] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/13
- [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/13
- [PATCH 06/85] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/13
- [PATCH 08/85] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/13
- [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 10/85] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/13
- [PATCH 07/85] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 11/85] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/13
- [PATCH 12/85] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/13
- [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond,
Richard Henderson <=
- [PATCH 14/85] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/13
- [PATCH 15/85] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 18/85] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 17/85] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/13
- [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/13
- [PATCH 22/85] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 26/85] target/sparc: Move MULX to decodetree, Richard Henderson, 2023/10/13
- [PATCH 23/85] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/13