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[PATCH 23/85] target/sparc: Move WRTBR, WRHPR to decodetree
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From: |
Richard Henderson |
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Subject: |
[PATCH 23/85] target/sparc: Move WRTBR, WRHPR to decodetree |
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Date: |
Fri, 13 Oct 2023 14:27:44 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 9 ++++
target/sparc/translate.c | 110 +++++++++++++++++++-------------------
2 files changed, 65 insertions(+), 54 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index b61926d278..0425764973 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -145,3 +145,12 @@ WRPR_strand_status 10 11010 110010 ..... . .............
@n_r_ri
FLUSHW 10 00000 101011 00000 0 0000000000000
RDTBR 10 rd:5 101011 00000 0 0000000000000
}
+
+{
+ WRTBR 10 00000 110011 ..... . ............. @n_r_ri
+ WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri
+}
+# WRHPR_htstate
+WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
+WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
+WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 4b4ca04d62..efb3c7c570 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4000,6 +4000,61 @@ static void do_wrssr(DisasContext *dc, TCGv src)
TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr)
+TRANS(WRTBR, 32, do_wr_special, a, supervisor(dc), do_wrtba)
+
+static void do_wrhpstate(DisasContext *dc, TCGv src)
+{
+#ifdef TARGET_SPARC64
+ tcg_gen_st_i64(src, tcg_env, offsetof(CPUSPARCState, hpstate));
+ dc->base.is_jmp = DISAS_EXIT;
+#else
+ g_assert_not_reached();
+#endif
+}
+
+TRANS(WRHPR_hpstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhpstate)
+
+static void do_wrhintp(DisasContext *dc, TCGv src)
+{
+#ifdef TARGET_SPARC64
+ tcg_gen_mov_tl(cpu_hintp, src);
+#else
+ g_assert_not_reached();
+#endif
+}
+
+TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp)
+
+static void do_wrhtba(DisasContext *dc, TCGv src)
+{
+#ifdef TARGET_SPARC64
+ tcg_gen_mov_tl(cpu_htba, src);
+#else
+ g_assert_not_reached();
+#endif
+}
+
+TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba)
+
+static void do_wrhstick_cmpr(DisasContext *dc, TCGv src)
+{
+#ifdef TARGET_SPARC64
+ TCGv_ptr r_tickptr = tcg_temp_new_ptr();
+
+ tcg_gen_mov_tl(cpu_hstick_cmpr, src);
+ tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, hstick));
+ translator_io_start(&dc->base);
+ gen_helper_tick_set_limit(r_tickptr, cpu_hstick_cmpr);
+ /* End TB to handle timer interrupt */
+ dc->base.is_jmp = DISAS_EXIT;
+#else
+ g_assert_not_reached();
+#endif
+}
+
+TRANS(WRHPR_hstick_cmpr, HYPV, do_wr_special, a, hypervisor(dc),
+ do_wrhstick_cmpr)
+
static bool do_saved_restored(DisasContext *dc, void (*func)(TCGv_env))
{
if (!supervisor(dc)) {
@@ -4681,63 +4736,10 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
#endif
case 0x30:
goto illegal_insn; /* WRASR in decodetree */
-#if !defined(CONFIG_USER_ONLY)
case 0x32:
goto illegal_insn; /* WRPR in decodetree */
case 0x33: /* wrtbr, UA2005 wrhpr */
- {
-#ifndef TARGET_SPARC64
- if (!supervisor(dc))
- goto priv_insn;
- tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
-#else
- CHECK_IU_FEATURE(dc, HYPV);
- if (!hypervisor(dc))
- goto priv_insn;
- cpu_tmp0 = tcg_temp_new();
- tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
- switch (rd) {
- case 0: // hpstate
- tcg_gen_st_i64(cpu_tmp0, tcg_env,
- offsetof(CPUSPARCState,
- hpstate));
- save_state(dc);
- gen_op_next_insn();
- tcg_gen_exit_tb(NULL, 0);
- dc->base.is_jmp = DISAS_NORETURN;
- break;
- case 1: // htstate
- // XXX gen_op_wrhtstate();
- break;
- case 3: // hintp
- tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
- break;
- case 5: // htba
- tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
- break;
- case 31: // hstick_cmpr
- {
- TCGv_ptr r_tickptr;
-
- tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
- r_tickptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tickptr, tcg_env,
- offsetof(CPUSPARCState,
hstick));
- translator_io_start(&dc->base);
- gen_helper_tick_set_limit(r_tickptr,
- cpu_hstick_cmpr);
- /* End TB to handle timer interrupt */
- dc->base.is_jmp = DISAS_EXIT;
- }
- break;
- case 6: // hver readonly
- default:
- goto illegal_insn;
- }
-#endif
- }
- break;
-#endif
+ goto illegal_insn; /* WRTBR, WRHPR in decodetree */
#ifdef TARGET_SPARC64
case 0x2c: /* V9 movcc */
{
--
2.34.1
- [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond, (continued)
- [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/13
- [PATCH 14/85] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/13
- [PATCH 15/85] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 18/85] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 17/85] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/13
- [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/13
- [PATCH 22/85] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 26/85] target/sparc: Move MULX to decodetree, Richard Henderson, 2023/10/13
- [PATCH 23/85] target/sparc: Move WRTBR, WRHPR to decodetree,
Richard Henderson <=
- [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/13
- [PATCH 29/85] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/13
- [PATCH 30/85] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/13
- [PATCH 34/85] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/13
- [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 20/85] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 25/85] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/13
- [PATCH 24/85] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/13
- [PATCH 27/85] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/13
- [PATCH 28/85] target/sparc: Move SUBC to decodetree, Richard Henderson, 2023/10/13