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[PATCH 18/20] target/sparc: Discard cpu_cond at the end of each insn
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From: |
Richard Henderson |
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Subject: |
[PATCH 18/20] target/sparc: Discard cpu_cond at the end of each insn |
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Date: |
Mon, 16 Oct 2023 23:41:07 -0700 |
If the insn raises no exceptions, there will be no path in which
cpu_cond is used, and so the computation may be optimized away.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index bdf1753a65..9f53e703e6 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -174,6 +174,7 @@ typedef struct DisasContext {
target_ulong jump_pc[2];
int mem_idx;
+ bool cpu_cond_live;
bool fpu_enabled;
bool address_mask_32bit;
#ifndef CONFIG_USER_ONLY
@@ -850,6 +851,19 @@ static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned
int fcc_offset)
tcg_gen_xori_tl(dst, dst, 0x1);
}
+static void finishing_insn(DisasContext *dc)
+{
+ /*
+ * From here, there is no future path through an unwinding exception.
+ * If the current insn cannot raise an exception, the computation of
+ * cpu_cond may be able to be elided.
+ */
+ if (dc->cpu_cond_live) {
+ tcg_gen_discard_tl(cpu_cond);
+ dc->cpu_cond_live = false;
+ }
+}
+
static void gen_generic_branch(DisasContext *dc)
{
TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]);
@@ -896,6 +910,7 @@ static void save_state(DisasContext *dc)
static void gen_exception(DisasContext *dc, int which)
{
+ finishing_insn(dc);
save_state(dc);
gen_helper_raise_exception(tcg_env, tcg_constant_i32(which));
dc->base.is_jmp = DISAS_NORETURN;
@@ -937,6 +952,8 @@ static void gen_check_align(DisasContext *dc, TCGv addr,
int mask)
static void gen_mov_pc_npc(DisasContext *dc)
{
+ finishing_insn(dc);
+
if (dc->npc & 3) {
switch (dc->npc) {
case JUMP_PC:
@@ -2247,6 +2264,8 @@ static bool advance_pc(DisasContext *dc)
{
TCGLabel *l1;
+ finishing_insn(dc);
+
if (dc->npc & 3) {
switch (dc->npc) {
case DYNAMIC_PC:
@@ -2290,6 +2309,8 @@ static bool advance_jump_cond(DisasContext *dc,
DisasCompare *cmp,
{
target_ulong npc = dc->npc;
+ finishing_insn(dc);
+
if (cmp->cond == TCG_COND_ALWAYS) {
if (annul) {
dc->pc = dest;
@@ -2354,6 +2375,7 @@ static bool advance_jump_cond(DisasContext *dc,
DisasCompare *cmp,
} else {
tcg_gen_setcondi_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
}
+ dc->cpu_cond_live = true;
}
}
return true;
@@ -2520,6 +2542,8 @@ static bool trans_Tcc(DisasContext *dc, arg_Tcc *a)
tcg_gen_addi_i32(trap, trap, TT_TRAP);
}
+ finishing_insn(dc);
+
/* Trap always. */
if (a->cond == 8) {
save_state(dc);
@@ -3198,6 +3222,7 @@ TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc),
do_wrstick_cmpr)
static void do_wrpowerdown(DisasContext *dc, TCGv src)
{
+ finishing_insn(dc);
save_state(dc);
gen_helper_power_down(tcg_env);
}
@@ -5148,6 +5173,8 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
DisasDelayException *e, *e_next;
bool may_lookup;
+ finishing_insn(dc);
+
switch (dc->base.is_jmp) {
case DISAS_NEXT:
case DISAS_TOO_MANY:
--
2.34.1
- [PATCH 00/20] target/sparc: Cleanup condition codes etc, Richard Henderson, 2023/10/17
- [PATCH 01/20] target/sparc: Introduce cpu_put_psr_icc, Richard Henderson, 2023/10/17
- [PATCH 02/20] target/sparc: Split psr and xcc into components, Richard Henderson, 2023/10/17
- [PATCH 03/20] target/sparc: Remove CC_OP_DIV, Richard Henderson, 2023/10/17
- [PATCH 04/20] target/sparc: Remove CC_OP_LOGIC, Richard Henderson, 2023/10/17
- [PATCH 05/20] target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD, Richard Henderson, 2023/10/17
- [PATCH 07/20] target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV, Richard Henderson, 2023/10/17
- [PATCH 09/20] target/sparc: Remove DisasCompare.is_bool, Richard Henderson, 2023/10/17
- [PATCH 08/20] target/sparc: Remove CC_OP leftovers, Richard Henderson, 2023/10/17
- [PATCH 12/20] target/sparc: Do flush_cond in advance_jump_cond, Richard Henderson, 2023/10/17
- [PATCH 18/20] target/sparc: Discard cpu_cond at the end of each insn,
Richard Henderson <=
- [PATCH 16/20] target/sparc: Merge gen_op_next_insn into only caller, Richard Henderson, 2023/10/17
- [PATCH 19/20] target/sparc: Implement UDIVX and SDIVX inline, Richard Henderson, 2023/10/17
- [PATCH 20/20] target/sparc: Implement UDIV inline, Richard Henderson, 2023/10/17
- [PATCH 13/20] target/sparc: Merge gen_branch2 into advance_pc, Richard Henderson, 2023/10/17
- [PATCH 15/20] target/sparc: Use DISAS_EXIT in do_wrpsr, Richard Henderson, 2023/10/17
- [PATCH 17/20] target/sparc: Record entire jump condition in DisasContext, Richard Henderson, 2023/10/17
- [PATCH 06/20] target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB, Richard Henderson, 2023/10/17
- [PATCH 10/20] target/sparc: Change DisasCompare.c2 to int, Richard Henderson, 2023/10/17
- [PATCH 11/20] target/sparc: Always copy conditions into a new temporary, Richard Henderson, 2023/10/17
- [PATCH 14/20] target/sparc: Merge advance_jump_uncond_{never, always} into advance_jump_cond, Richard Henderson, 2023/10/17