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[PULL v3 33/62] hw/isa/piix3: Create USB controller in host device
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From: |
Michael S. Tsirkin |
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Subject: |
[PULL v3 33/62] hw/isa/piix3: Create USB controller in host device |
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Date: |
Sun, 22 Oct 2023 05:24:16 -0400 |
From: Bernhard Beschow <shentey@gmail.com>
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-13-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 4 ++++
hw/i386/pc_piix.c | 7 ++-----
hw/isa/piix3.c | 16 ++++++++++++++++
hw/isa/Kconfig | 1 +
4 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 1daeff397c..5cd866f1f2 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci_device.h"
#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -54,12 +55,15 @@ struct PIIXState {
MC146818RtcState rtc;
PCIIDEState ide;
+ UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+ bool has_usb;
};
typedef struct PIIXState PIIX3State;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c98a997482..8dcd6851d0 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -51,7 +51,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -265,6 +264,8 @@ static void pc_init1(MachineState *machine,
size_t i;
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+ object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), &error_abort);
dev = DEVICE(pci_dev);
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
@@ -359,10 +360,6 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && machine_usb(machine)) {
- pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
- }
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 3f1dabade0..aebc0da23b 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -298,6 +298,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
return;
}
+
+ /* USB */
+ if (d->has_usb) {
+ object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
+ TYPE_PIIX3_USB_UHCI);
+ qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -332,6 +342,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
+static Property pci_piix3_props[] = {
+ DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -352,6 +367,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 28345edbb3..1076df69ca 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -37,6 +37,7 @@ config PIIX3
select IDE_PIIX
select ISA_BUS
select MC146818RTC
+ select USB_UHCI
config PIIX4
bool
--
MST
- [PULL v3 20/62] timer/i8254: Fix one shot PIT mode, (continued)
- [PULL v3 20/62] timer/i8254: Fix one shot PIT mode, Michael S. Tsirkin, 2023/10/22
- [PULL v3 24/62] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize(), Michael S. Tsirkin, 2023/10/22
- [PULL v3 26/62] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property, Michael S. Tsirkin, 2023/10/22
- [PULL v3 25/62] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS, Michael S. Tsirkin, 2023/10/22
- [PULL v3 27/62] hw/i386/pc_piix: Remove redundant "piix3" variable, Michael S. Tsirkin, 2023/10/22
- [PULL v3 28/62] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in", Michael S. Tsirkin, 2023/10/22
- [PULL v3 29/62] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize(), Michael S. Tsirkin, 2023/10/22
- [PULL v3 31/62] hw/i386/pc: Wire RTC ISA IRQs in south bridges, Michael S. Tsirkin, 2023/10/22
- [PULL v3 30/62] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device, Michael S. Tsirkin, 2023/10/22
- [PULL v3 32/62] hw/isa/piix3: Create IDE controller in host device, Michael S. Tsirkin, 2023/10/22
- [PULL v3 33/62] hw/isa/piix3: Create USB controller in host device,
Michael S. Tsirkin <=
- [PULL v3 34/62] hw/isa/piix3: Create power management controller in host device, Michael S. Tsirkin, 2023/10/22
- [PULL v3 35/62] hw/isa/piix3: Drop the "3" from PIIX base class name, Michael S. Tsirkin, 2023/10/22
- [PULL v3 36/62] hw/isa/piix4: Remove unused inbound ISA interrupt lines, Michael S. Tsirkin, 2023/10/22
- [PULL v3 37/62] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in", Michael S. Tsirkin, 2023/10/22
- [PULL v3 40/62] hw/isa/piix3: Merge hw/isa/piix4.c, Michael S. Tsirkin, 2023/10/22
- [PULL v3 41/62] hw/isa/piix: Allow for optional PIC creation in PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 38/62] hw/isa/piix4: Rename reset control operations to match PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 39/62] hw/isa/piix4: Reuse struct PIIXState from PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 42/62] hw/isa/piix: Allow for optional PIT creation in PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 43/62] hw/isa/piix: Harmonize names of reset control memory regions, Michael S. Tsirkin, 2023/10/22