[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v3 36/62] hw/isa/piix4: Remove unused inbound ISA interrupt lines
|
From: |
Michael S. Tsirkin |
|
Subject: |
[PULL v3 36/62] hw/isa/piix4: Remove unused inbound ISA interrupt lines |
|
Date: |
Sun, 22 Oct 2023 05:24:29 -0400 |
From: Bernhard Beschow <shentey@gmail.com>
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines. PIIX3 doesn't expose such interrupt lines
either, so remove them for PIIX4 for simplicity and consistency.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-16-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/isa/piix4.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index e0b149f8eb..3c3c7a094c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -148,12 +148,6 @@ static void piix4_request_i8259_irq(void *opaque, int irq,
int level)
qemu_set_irq(s->cpu_intr, level);
}
-static void piix4_set_i8259_irq(void *opaque, int irq, int level)
-{
- PIIX4State *s = opaque;
- qemu_set_irq(s->isa[irq], level);
-}
-
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
@@ -197,8 +191,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
- qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
- "isa", ISA_NUM_IRQS);
qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
"intr", 1);
--
MST
- [PULL v3 25/62] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS, (continued)
- [PULL v3 25/62] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS, Michael S. Tsirkin, 2023/10/22
- [PULL v3 27/62] hw/i386/pc_piix: Remove redundant "piix3" variable, Michael S. Tsirkin, 2023/10/22
- [PULL v3 28/62] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in", Michael S. Tsirkin, 2023/10/22
- [PULL v3 29/62] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize(), Michael S. Tsirkin, 2023/10/22
- [PULL v3 31/62] hw/i386/pc: Wire RTC ISA IRQs in south bridges, Michael S. Tsirkin, 2023/10/22
- [PULL v3 30/62] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device, Michael S. Tsirkin, 2023/10/22
- [PULL v3 32/62] hw/isa/piix3: Create IDE controller in host device, Michael S. Tsirkin, 2023/10/22
- [PULL v3 33/62] hw/isa/piix3: Create USB controller in host device, Michael S. Tsirkin, 2023/10/22
- [PULL v3 34/62] hw/isa/piix3: Create power management controller in host device, Michael S. Tsirkin, 2023/10/22
- [PULL v3 35/62] hw/isa/piix3: Drop the "3" from PIIX base class name, Michael S. Tsirkin, 2023/10/22
- [PULL v3 36/62] hw/isa/piix4: Remove unused inbound ISA interrupt lines,
Michael S. Tsirkin <=
- [PULL v3 37/62] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in", Michael S. Tsirkin, 2023/10/22
- [PULL v3 40/62] hw/isa/piix3: Merge hw/isa/piix4.c, Michael S. Tsirkin, 2023/10/22
- [PULL v3 41/62] hw/isa/piix: Allow for optional PIC creation in PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 38/62] hw/isa/piix4: Rename reset control operations to match PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 39/62] hw/isa/piix4: Reuse struct PIIXState from PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 42/62] hw/isa/piix: Allow for optional PIT creation in PIIX3, Michael S. Tsirkin, 2023/10/22
- [PULL v3 43/62] hw/isa/piix: Harmonize names of reset control memory regions, Michael S. Tsirkin, 2023/10/22
- [PULL v3 44/62] hw/isa/piix: Share PIIX3's base class with PIIX4, Michael S. Tsirkin, 2023/10/22
- [PULL v3 45/62] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4, Michael S. Tsirkin, 2023/10/22
- [PULL v3 46/62] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering, Michael S. Tsirkin, 2023/10/22